Perkins Coie LLP
Semiconductor device with a time multiplexing mechanism for size efficiency
A memory device includes a first set of data input/output (I/O) devices configured to communicate a first portion of a data unit to or from an external controller; a second set of data I/O devices configured to communicate a second portion of the data unit to or from the external controller; a data control circuit can share the internal global data lines by multiplexing the timings of the first and second sets of data I/O devices, the data control circuit configured to route the data unit according to a data operation corresponding to the data unit; and a shared data bus coupling both the first set of data I/O devices and the second set of data I/O devices to the data control circuit, the shared data bus configured to relay both the first portion and the second portion of the data unit.
Micron Technology, Inc.
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Michael V. Ravi Kiran
Ho Kandikonda