Finnegan, Henderson, Farabow, Garrett & Dunner
MOS Integrated logic circuit device with improved switching speed characteristics
 A semiconductor integrated circuit device, which comprises: PA1 transistors constituting a plurality of series-connected logic circuits, wherein some of the mutually-facing or paired transistors of every two adjacent series-connected logic circuits or at least one pair thereof are so connected as to span said two adjacent circuits with a common gate provided between said paired transistors; PA1 conductors for connecting the source electrodes and/or the drain electrodes of said spanning paired transistors; and PA1 a plurality of signal generators for supplying required signals to the respective transistors, and whereby a MOS type logic circuit constructed by arranging those of the transistors which are supplied with a synchronizing signal closer to the output terminal than those of the transistors which are supplied with an input signal can be accelerated in operation. 
Tokyo Shibaura Denki Kabushiki Kaisha
H H
H03K H03K
inventional inventional
Kenji Yasoji
Matsuo Suzuki