JW Law Group
Methods and apparatus for providing a clock fabric for an FPGA organized in multiple clock regions
A field-programmable gate array (“FPGA”) contains a configurable semiconductor organized in multiple clock regions with a clock fabric for facilitating user-defined logic functions. The clock fabric provides a set of regional clock signals (“RCSs”) generated from a clock source with a high clock signal quality (“CSQ”) for clocking logic blocks in a clock region. Also, a set of neighboring clock signals (“NCSs”) or inter-regional clock signals are generated from a neighboring clock source(s) for clocking logic blocks in two neighboring regions. In addition, the clock fabric is operable to provide secondary clock signals (“SCSs”) generated from the RCSs with a low CSQ for clocking logic blocks with less time-sensitive logic operations.
GOWIN Semiconductor Corporation
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inventional inventional inventional
Diwakar Chienkuang Tianping Xiaozhi Jinghui Tianxin Ning Zhenyu Jianhua
Chopperla Chen Wang Lin Zhu Wang Song Gu Liu