Haynes and Boone, LLP
Cut metal gate process for reducing transistor spacing
A method includes providing a structure having a substrate and first and second fins over the substrate and oriented lengthwise generally along a first direction; epitaxially growing semiconductor source/drain (S/D) features over the first and second fins, wherein a first semiconductor S/D feature over the first fin merges with a second semiconductor S/D feature over the second fin; and performing a first etching process to an area between the first and second fins, wherein the first etching process separates the first and second semiconductor S/D features.
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
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Chang-Yun Ming-Chang Hung-Kai Hsien-Chin
Chang Wen Chen Lin