Blakeley, Sokoloff, Taylor & Zafman
Memory circuitry having bus interface for receiving information in packets and access time registers
 An interfacing circuitry for a semiconductor circuit of a computer system selects the semiconductor circuit for a device operation in accordance with data, addresses, and control information received from a multiline bus of the computer system in a form of packets. The computer system has a plurality of semiconductor circuits. The interfacing circuitry is coupled to the multiline bus. The multiline bus has a total number of lines less than a total number of bits in any single address. The interfacing circuitry resides inside the semiconductor circuit and includes a decoder for decoding the packets received to identify the data, addresses, and control information. A control logic circuitry is coupled to the decoder circuitry for controlling device operation of the first semiconductor circuit in accordance with the data, addresses, and control information received. A register circuitry is coupled to the decoder and the control logic circuitry for storing a first value corresponding to a first predetermined time period during which the interfacing circuitry must wait before transmitting reply information through the multiline bus in response to the data, addresses, and control information received. The register circuitry applies the first value to the control logic circuitry to cause the control logic circuitry to wait for the first predetermined time period before accessing the multiline bus for transmitting the reply information. 
Rambus, Inc.
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Mark Michael
Horowitz Farmwald