Low power flip-flop circuit
A 24-transistor D flip-flop circuit operates in a sampling mode when a clock signal has a first voltage state, and a holding mode when the clock signal has a second voltage state. The flip-flop circuit includes an internal control node coupled to a reference voltage node by way of a transistor controllable to couple the internal control node to the reference voltage node when the clock signal has the second voltage state. The flip-flop has very low power dissipation as it includes a 4-transistor change-sense component to detect changes in input data. The change-sense component is coupled in series with the transistor and receives an indication of an input voltage state of the flip-flop circuit and an indication of an output voltage state of the flip-flop circuit, and inhibits toggling of the internal control node if the indicated input voltage state and the indicated output voltage state are the same.
FREESCALE SEMICONDUCTOR, INC.
H H H
H03K H03K H03K
inventional inventional inventional
Alan Yeow Khai Van-Loi Tae-Hyoung Juhui
Chang Le Kim Li