Jianq Chyun IP Office
Delay locked loop
In a delay locked loop, a phase detector compares the phases of an input signal and an output signal; a delay line delays the input signal, wherein the delay line includes a plurality of unit delay elements connected in series and the value of the unit delay of each of the unit delay elements is adjusted by a control signal; a multiplexer selects a number of delay stages of the unit delay elements according to the phase comparison result and generates the output signal. The control signal is related to a clock information signal. When the input signal is high frequency, the value of the unit delay would be small; and when the input signal is low frequency, the value of the unit delay would be large.
Nanya Technology Corporation
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Wei-Li
Liu