Jianq Chyun IP Office
Memory apparatus
The present disclosure provides a memory apparatus including a memory cell array, a plurality of sense amplifiers, at least one first comparing circuit, and a plurality of second comparing circuit. The memory cell array includes a plurality of memory cells. Each of the sense amplifier generates a data signal and an inverted data signal according to a bit line signal and an inverted bit line signal. The first comparing circuits compares the data signals of first and second sense amplifiers with a first tag to generate a first comparing result. The second comparing circuits respectively compare a plurality of second tags with the data signals of the sense amplifiers to respectively generate a plurality of second comparing results.
National Tsing Hua University
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Tien-Fu Keng-Hao Chia-Yin Meng-Fan Yu-Lin
Chen Yang Li Chang Chen