Stanzione & Kim, LLP
Isolation layer structure, method of forming the same and method of manufacturing a semiconductor device including the same
An isolation layer structure includes first to fourth oxide layer patterns. The first and third oxide layer patterns are sequentially formed in a first trench defined by a first recessed top surface of a substrate and sidewalls of gate structures on the substrate in a first region. The first trench has a first width, and the first and third oxide layer patterns have no void therein. The second and fourth oxide layer patterns are sequentially formed in a second trench defined by a second recessed top surface of the substrate and sidewalls of gate structures on the substrate in a second region. The second trench has a second width larger than the first width, and the fourth oxide layer pattern has a void therein.
Samsung Electronics Co., Ltd.
H
H01L
inventional
Kyu-Tae Dae-Young Il-Woo Seung-Bae Min Ju-Wan
Na Kwak Kim Park Kim Kim