J. C. Patents
Stacked chip scale package
A stacked chip scale package. The stacked chip scale package has a substrate having mounting pads arranged to lie close to the rectangular sides. A smaller silicon chip is stacked on the active surface of a larger silicon chip and the larger silicon chip rest on the substrate. The mounting pads on the substrate are distributed around the periphery of the lower silicon chip. Both the upper silicon chip and the lower silicon chip have only one pair of opposite sides having bonding pads. The pair of edges of the upper silicon chip with bonding pads nearby is parallel to the pair of edges of the lower silicon chip without bonding pads. The bonding pads on the upper chip and the lower chip are electrically connected to their neighboring mounting pads through conductive wires. The conductive wires, the upper silicon chip, the lower silicon chip and a portion of the substrate are enclosed by packaging material.
Advanced Semiconductor Engineering, Inc.
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Sung-Fei Jian-Wen
Wang Chen