Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Semiconductor device
 Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions 10 to 15 and 21 to 23 and polysilicon regions 31 to 42) of a memory cell for one memory cell unit of a memory cell array region 1 is identical to that of a dummy cell of a peripheral dummy cell region 3, and both patterns present a line symmetrical relationship with respect to a boundary line BC1. In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region 1 is identical to that of a dummy cell of a power wiring region 2, and both patterns present a line symmetrical relationship with respect to a boundary line BC2. 
Mitsubishi Denki Kabushiki Kaisha
H H
H01L H01L
inventional inventional
Yasunobu Niichi Tetsuya Chikayoshi
Nakase Itoh Watanabe Morishima