Eschweiler & Associates, LLC
Package and method for integration of heterogeneous integrated circuits
A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip.
Taiwan Semiconductor Manufacturing Co., Ltd.
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Jui Hsieh Ying-Hao Chun-Hao Wan-Yu Tien-Yu Kuo-Chung
Lai Kuo Tseng Lee Huang Yee