Duane Morris LLP
PVT-free calibration function using a doubler circuit for TDC resolution in ADPLL applications
An ADPLL circuit includes a time-to-digital converter (TDC) configured to generate a signal indicative of a phase difference between a first signal and a reference signal and a doubler electrically coupled to the TDC. The doubler is configured to receive a first voltage signal and generate a second voltage signal. The second voltage signal is provided to a voltage input of the TDC. The TDC is configured to generate one or more control signals for the doubler to adjust the second voltage signal.
Taiwan Semiconductor Manufacturing Co., Ltd.
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Robert Bogdan Seyednaser Huan-Neng Feng Wei Chewn-Pu Lan-Chou
Staszewski Pourmousavian Chen Kuo Jou Cho