Lowe Hauptman & Ham LLP
System and methods for converting planar design to FinFET design
A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.
Taiwan Semiconductor Manufacturing Company, Ltd.
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additional additional inventional inventional
Cheok-Kei Chih-Sheng Hsiao-Hui Yu-Ning Chien-Wen Yi-Tang Clement Hsingjen Shu-Yu
Lei Chang Chen Chang Chen Lin Wann Chen