Conley, Rose & Tayon
Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock
 A superscalar microprocessor employing a branch prediction array update unit is provided. The branch prediction array update unit collects the update prediction information for each branch misprediction or external fetch. When a fetch address is presented for branch prediction, the fetch address is compared to the update address stored in the update unit. If the addresses match, then the update prediction information is forwarded as the output of the array. If the addresses do not match, then the information stored in the indexed storage location is forwarded as the output of the array. When the next external fetch begins or misprediction is detected, the update is written into the branch prediction array. The update unit allows for a single-ported array implementation of the branch prediction array while still maintaining the operational aspects of the dual-ported array implementation, as well as allowing for speculative branch prediction update. 
Advanced Micro Devices, Inc.
G G G
G06F G06F G06F
inventional inventional inventional
Thang M. David B.
Tran Witt