Staas & Halsey
Complementary metal-insulated semiconductor memory decoder
 A complementary metal-insulated semiconductor (CMIS) which is useful for a highly integrated large-capacity ROM or RAM. The CMIS memory decoder specifies each set of 2.sup.m (m is positive integer) word lines of a memory to be accessed by the CMIS memory decoder. The CMIS memory decoder includes both 2.sup.m CMIS inverters per each set of the 2.sup.m word lines and also 2.sup.m -1 pull-down transistors per each word line, the pull-down transistors being connected between ground and the corresponding word lines, the remaining 2.sup.m -1 word lines being connected to these pull-down transistors at their gates. 
Fujitsu Limited
G G H
G11C G11C H03M
inventional inventional inventional
Masanori Yasuo
Nagasawa Suzuki