Schwegman, Lundberg & Woessner, P.A.
High performance queue implementations in multiprocessor systems
Systems and methods provide a single reader single writer (SRSW) queue structure having entries that can be concurrently accessed in an atomic manner with a single memory access. The SRSW queues may be combined to create more complicated queues, including multiple reader single writer (MRSW), single reader multiple writer (SRMW), and multiple reader multiple writer (MRMW) queues.
Intel Corporation
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Xiao-Feng Dz-ching
Li Ju