Staas & Halsey LLP
Semiconductor devices having multiple memories
A semiconductor device having multiple memory circuits of varying sizes includes scan test circuitry that enables the memories to be simultaneous loaded with pattern data and tested. A first memory circuit has a first memory, a first address scan chain that receives serial scan-in address data and generates a first address signal, and a first data scan chain that receives serial scan-in data and generates a first data input signal. A second memory circuit has a second memory, a second address scan chain that receives the serial scan-in address data and generates a second address signal, and a second data scan chain that receives the serial scan-in data and generates a second data input signal.
Fujitsu Limited
G G G G G G
G11C G11C G11C G01R G01R G01R
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Kiminori Masahiko Yasuhiro Tetsuya Hideaki Terumi
Kato Sudo Kawakami Hiramatsu Nakahara Yoshimura