Renaissance IP Law Group LLP
Method of forming internal dielectric spacers for horizontal nanosheet FET architectures
A method to form a nanosheet stack for a semiconductor device includes forming a stack of a plurality of sacrificial layers and at least one channel layer on an underlayer in which a sacrificial layer is in contact with the underlayer, each channel layer being in contact with at least one sacrificial layer, the sacrificial layers are formed from SiGe and the at least one channel layer is formed from Si; forming at least one source/drain trench region in the stack to expose surfaces of the SiGe sacrificial layers and a surface of the at least one Si channel layer; and oxidizing the exposed surfaces of the SiGe sacrificial layers and the exposed surface of the at least one Si layer in an environment of wet oxygen, or ozone and UV.
SAMSUNG ELECTRONICS CO., LTD.
H H H H H H H H H H H H
H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L
inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional
Dharmendar Reddy Mark S. Wei-E Borna J. Joon Goo
Palle Rodder Wang Obradovic Hong