Scully, Scott, Murphy & Presser, P.C.
Non-conformal stress liner for enhanced MOSFET performance
A semiconductor device is provided wherein at least one offset spacer is reduced and a non-conformal stress liner is thereafter deposited. By depositing the non-conformal stress liner in accordance with the present invention in close stress proximity to the FET, the carrier mobility and the performance of said device is significantly enhanced. The present invention is her directed to a method of fabricating said semiconductor device.
International Business Machines Corporation Samsung Electronics Co., Ltd.
H H
H01L H01L
inventional inventional
Thomas Sunfei Jun Jung
Dyer Fang Kim