Allegretti, Newitt, Witcoff & McAndrews, Ltd.
Central processing unit
 A central processing unit capable of executing the IBM System/370 Universal Instruction Set is disclosed. The instruction set establishes the functional specifications for the processing unit, features of which include: 8-bit (byte) alphanumeric coding, 4-bit packed decimal coding (2 digits per byte), two's complement fixed-point binary arithmetic, two levels of indexing, sixteen 32-bit (4 byte) addressable general registers, four 64-bit floating point registers, and program status word and control registers. Principal features of the hardware architecture include the use of a single main data/instruction bus, transfers to and from the main bus being made under encoded microprogram control, and placement of the fixed-point binary arithmetic logic unit elements and the associated sixteen general registers on a single cascaded group of LSIC chips which operate under control of the microcode. The microcode store is addressed by a microprogram control unit which includes a control counter stack memory and a return address stack memory permitting up to sixteen levels of microprogram sub-routines to be used. 
Signetics Corporation
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inventional inventional
Jared A. Jimmy E. Lauren F. Robert V.
Anderson Braun Yazolino Van Gelder