Jaffery, Watson, Mendonsa & Hamilton LLP
Extend GPU/CPU coherency to multi-GPU cores
In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.
INTEL CORPORATION
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Feng Kamal Joydeep Rajkishore Chandrasekaran Narayan Ben J. Balaji Altug Justin E. Prasoonkumar Abhishek R. Eriko Sara S. Nicolas C. John C. Tsung-Han
Chen Sinha Ray Barik Sakthivel Srinivasa Ashbaugh Vembu Koker Gottschlich Surti Appu Nurvitadhi Baghsorkhi Galoppo Von Borries Weast Lin