Fletcher Yoder, P.C.
Systems and methods for improving fuse systems in memory devices
A memory device includes a memory bank accessible via a plurality of memory addresses. The memory device further includes a fuse array comprising a plurality of fuses. The memory device additionally includes a first plurality of local fuse latches disposed outside of the fuse array and configured to provide redundancy for the plurality of memory addresses. The memory device also includes a fuse array broadcasting system comprising an N-bit bus system, wherein the N-bit bus system is communicatively coupled to the fuse array and to the first plurality of local fuse latches, and wherein the fuse array broadcasting system is configured to communicate fuse data from the fuse array to the first plurality of local fuse latches via the N-bit bus system.
Micron Technology, Inc.
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Scott E. Yu-Feng John E.
Smith Chen Riley