Marger, Johnson, & McCollom, P.C.
Redundancy circuit for memory devices having high frequency addressing cycles
 A redundancy circuit for activating redundant memory cells when a semiconductor memory device is found to have defective memory cells, which redundancy circuit comprises, in order to overcome the problems of an address reset and a precharging of the first node which determines the redundancy addressing output signal of the redundancy circuit, additional switching circuit which is controlled by a clock signal of the memory device being made to be connected between a ground node and a switching circuit connected to a plurality of fuses, and a precharging circuit for precharging the first node to a high voltage level being made to also controlled by the clock signal. 
Samsung Electronics, Co., Ltd.
G
G11C
inventional
Seung-Hun
Lee