Skjerven, Morrill, MacPherson Franklin & Friel
Multi-port memory cells and memory with parallel data initialization
 A static RAM memory cell with a plurality of input/output ports is disclosed including: a latch circuit which maintains complementary voltages at first and second nodes; a first output circuit which generates an output signal having an state inverted from the voltage of the first node; a second output circuit which generates an output signal having an state inverted from the voltage of the second node; a first transfer circuit for transferring the output signals from the first and second output circuits to a first sense amplifier in response to a first read control signal; a second transfer circuit for transferring the output signals from the first and second output circuits to a second sense amplifier in response to a second read control signal; a third transfer circuit for transferring an external voltage to the first node in response to a write control signal; and a reset circuit for resetting the latch circuit to initialize data in response to a reset signal. 
Samsung Electronics Co., Ltd.
G G
G11C G11C
inventional inventional
Jung-Kwon
Kim