McDermott Will & Emery LLP
Packet transmission/reception processor
If a packet processing controller at a consumer node has failed to process a received packet within a predetermined amount of time, a packet processing control timer detects a time-out and informs a CPU of that. In response, the CPU issues packet processing suspend instruction and packet transmit instruction for the controller by way of a register. In accordance with these instructions, the controller suspends the current packet processing and produces header and data for a WRS packet, which is transmitted to a producer node through a bus. In this manner, a packet can be processed without causing a time-out at the producer node.
Matsushita Electric Industrial Co., Ltd.
H H
H04L H04L
inventional inventional
Yoshihiro Hirotaka
Tabira Ito