Oblon, Fisher, Spivak, McClelland & Maier
Word line driver for use in a semiconductor memory
A word line driver for use in a dRAM. This word line driver comprises one npn bipolar transistor and four n-channel transistors. The bipolar transistor is connected between an "H"-level potential terminal and an output terminal. The first MOS transistor is connected in parallel to the bipolar transistor, and is driven by one output signal of a row decoder to supply an output at a sufficiently high "H" level to word lines. The third MOS transistor is coupled between the base and collector of the bipolar transistor, and its gate is connected to the gate of the first MOS transistor. The third MOS transistor supplies a sufficient base current to the base of the bipolar transistor when the word line driver outputs a potential at the "H" level. The second MOS transistor is coupled between the source of the first MOS transistor and a ground potential terminal, and the fourth MOS transistor is coupled between the source of the third MOS transistor and the ground potential terminal. The other output signal, which is complementary to the one output signal of the row decoder, is supplied to the gates of the second and fourth MOS transistors.
Kabushiki Kaisha Toshiba
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H03K G11C H03K H03K
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Shigeyoshi Koji
Watanabe Sakui