Beyer Weaver & Thomas
Silicide encapsulation of polysilicon gate and interconnect
 Provided is a method of forming a silicide layer on the top and sidewall surfaces of a polysilicon gate/interconnect in a MOS transistor and on the exposed surfaces of the source and drain regions of the transistor. Devices produced according to the present invention may have different types of silicide formed on their gate and their source/drain electrodes. The invention achieves the advantages of silicide encapsulation of a polysilicon gate in an MOS transistor while also providing silicidation of the source/drain regions of the transistor, thereby reducing electrode resistivity in the transistor and interconnect. 
LSI Logic Corporation
H H H H
H01L H01L H01L H01L
inventional inventional inventional additional
Ruggero Gary K. Yauh-Ching Subramanian
Castagnetti Giust Liu Ramesh