Schwegman, Lundberg, Woessner & Kluth, P.A.
Register rotation prediction and precomputation
Instruction-level parallelism in software pipelined loops is exploited by predicting future register rotations. A processor includes an architected current frame marker register and at least one unarchitected frame marker register. Register rotation prediction is achieved by setting the register rotation of future iterations of a software loop to be a function of the unarchitected frame marker registers. True data dependencies remain, but the dependencies caused solely by register renaming are removed. Dynamic predication is used to predicate instructions from future iterations, allowing them to be squashed if dependencies are later found. The register renaming that results from the prediction can be included in instructions in a buffer, or a renaming stage in an execution pipeline can perform the renaming.
Intel Corporation
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Hong Christopher J. Ralph John Yong-Fong Jamison Daniel M.
Wang Hughes Kling Shen Lee Collins Lavery