Fleshner & Kim
Output circuit for memory device
 An output circuit for a semiconductor memory device includes an output buffer for buffering an externally applied output enable signal and a signal outputted from a sense amplifier in accordance with the output enable signal, and an output driver having a CMOS inverter structure connected between a supply voltage and a ground voltage. The output driver includes two pairs of MOS transistors, each having a transistor of a different channel size connected in parallel with each other. When the sense amplifier carries out a sensing operation, the larger channel size MOS transistors are driven by a voltage from a feedback output terminal. When the sensing operation is completed, both pairs of MOS transistors are simultaneously driven in accordance with an output signal of the output buffer. The circuit increases a data signal output speed and decreases the output noise, by turning the data output signal into a completely tri-stated signal during a sensing operation of the sense amplifier. 
LG Semicon Co., Ltd.
G H
G11C H03K
inventional inventional
Yun Saing
Kim