Method for improving bit line to capacitor electrical failures on DRAM circuits using a wet etch-back to improve the bit-line-to-capacitor overlay margins
A method is described for making capacitor-under-bit line (CUB) DRAM cells with improved overlay margins between bit lines and capacitor top electrodes. After forming FETs for the memory cells, an interpolysilicon oxide (IPO) layer is deposited, and first and second plug contacts are formed in the IPO to the FET source/drain areas for capacitors and bit line contacts, respectively. A capacitor node oxide is deposited, and first openings are etched in which crown capacitor bottom electrodes are formed. After etching back the node oxide a thin interelectrode dielectric layer is formed and a conformal conducting layer is deposited to form capacitor top electrodes. A photoresist mask is used to etch openings in the conducting layer over the second plug contacts, and an isotropic etch is used to recess the openings under the mask to increase the spacing between the capacitor top electrodes and the bit line contacts to improve the overlay margin. The photoresist mask is removed and an interlevel dielectric (ILD) layer is deposited. Bit-line contact openings are etched in the ILD layer aligned over the recessed openings and in the node oxide to the second contact plugs. Bit-line contact plugs are formed extending through the recessed openings, and a first conducting layer is deposited and patterned to form bit lines and to complete the memory cells for the DRAM.
Taiwan Semiconductor Manufactoring Company
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Tse-Liang Hsiao-Hui Kuo-Chyuan Chung-Wei Min-Hsiung
Ying Tseng Tzeng Chang Chiang