McGinn & Gibb, P.C.
High efficiency redundancy scheme for semiconductor memory device
 A semiconductor memory device is provided that includes a plurality of normal memory cells, a device for activating the memory cells in response to an externally applied address and a plurality of redundant memory cells. A memory and comparison device may include a device for storing an address of a failed memory cell existing within a plurality of normal memory cells and a device for comparing the externally applied address with the failed memory cell address. A redundant memory cell selection device may select any one of a plurality of redundant memory cells in response to an output signal output from the memory and comparison device. A redundant memory cell activating device may activate the redundant memory cell, responsive to an output of the memory and comparison device. 
NEC Corporation
G
G11C
inventional
Mamoru
Fujita