Foley & Lardner
Apparatus having hierarchically arranged decoders concurrently decoding instructions and shifting instructions not ready for execution to vacant decoders higher in the hierarchy
 An apparatus for use with a computing device for executing instructions in a logical sequence according to a control program, comprises an instruction buffer of FIFO construction serially connected to a decoder buffer also of a FIFO construction. The decoder buffer includes a number of decoder units arranged in a hierarchical manner from a lowest-significance decoder unit to a highest-significance decoder unit in order to maintain the logical sequence of the instructions. The decoder units concurrently decode instructions transmitted from the instruction buffer and concurrently determine whether a corresponding decoded instruction is ready to be sent to an instruction executing unit. Each decoder unit is capable of sending a corresponding instruction to the instruction executing unit. Instructions ready to be sent are sent to the instruction executing unit, according to the logical sequence. Instructions not ready to be sent are shifted to higher-significance available vacant decoder units, while maintaining the logical sequence of the instructions. 
Advanced Micro Devices, Inc.
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Thang M.
Tran