Moser, Patterson & Sheridan, L.L.P.
Method and circuit configuration for multiple charge recycling during refresh operations in a DRAM device
Methods and circuit configurations for multiple recycling of charge during a refresh operation in a memory device, such as a dynamic random access memory (DRAM) device, are provided. Charge from one or more power lines of a first array of bit line sense amplifiers involved in a first refresh operation may be transferred to one or more power lines of at least second and third arrays of bit line sense amplifiers involved in subsequent refresh operations.
Infineon Technologies AG
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Jung Pill Jonghee
Kim Han