Brundidge & Stanger, P.C.
Logic circuit
A first current source generating a current I0+I when a control signal is in ‘H’ level and a current I0 when it is in ‘L’ level, a current mirror circuit transferring a current generated in the first current source and composed of first and second MOS transistors, and a second current source connected to the second transistor and generating I0+I are provided. Further, a node branched from a connection node between the second transistor and the second current source is formed, and a logic unit including a flip-flop circuit formed of a differential amplifier is driven through the node. The logic unit is in an active state when the control signal is in ‘H’ level and it is in an inactive state when the signal is in ‘L’ level. When the logic unit is in an active state, it processes a data input signal to generate data output signal.
Hitachi, Ltd.
H H
H03K H03K
inventional inventional
Hiroki Fumio
Yamashita Yuuki