Differential treatment to selectively avoid silicide formation on ESD I/O transistors in a salicide process
 Selective salicidation of source/drain regions of a transistor is accomplished by differentially treating a first subset of the source/drain regions to hinder formation of metal-silicide over the first subset of the source/drain regions. A metal layer is formed over the first subset of the source/drain regions and a second subset of the source/drain regions. The metal layer is annealed at a temperature such that the metal reacts to form metal-silicide over the second subset of the source/drain regions, but not over the first subset of the source/drain regions. The unreacted metal is stripped off over the first subset of the source/drain regions. In the preferred embodiment of the present invention, a second anneal is then performed to fully form metal-silicide over the second subset of the source/drain regions. 
VLSI Technology, Inc.
H
H01L
inventional
Tiao-Yuan
Huang