Staas & Halsey
Method of expressing a logic circuit
 A method of expressing a logic circuit for use in a multistage logic circuit optimizing process for performing removal or scale-down modification of redundant circuit parts without changing an output logic. A tree-structure binary decision diagram representing a permissible function or a logic function is created for determining the order of input variables of a multistage logic circuit, allocating an input variable of the first order to the root, allocating the other input variables to nodes, branching the root for each logic state (1, 0) that the input variable can assume, linking branches with nodes to which an input variable of the next order is allocated and linking branches with leaves providing logic (1, 0, don't care) or logic (1, 0) of each gate and net of the circuit. Two binary decision diagrams representing permissible functions intersect to terminate branches of input variables linked with the don't-care leaf to a 0 or 1 leaf, thereby merging gates. Two binary decision diagrams of the same type are traced from their respective roots in the direction of the same logic of each input variable. When respective leaves are reached, operational processing is performed on logic states of the leaves for each combination of logic states of the input variables. 
Fujitsu Limited
G
G06F
inventional
Masahiro Yusuke
Fujita Matsunaga