Haynes and Boone, LLP
Method of fabricating an integrated circuit with optimized pattern density uniformity
The present disclosure provides a method that includes receiving an IC design layout having main features and generating a plurality of space block layers to the IC design layout. The method also includes calculating main pattern density PD0 and dummy pattern density PDs of the IC design layout and calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for each of the space block layers according to the main pattern density and the dummy pattern density. The method further includes choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR and generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio. Additionally, the method includes forming a tape-out data of the modified IC design layout for IC fabrication.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Burn Jeng Shy-Jay Jyuh-Fuh Pei-Yi Wen-Chuan Cheng-Hung
Lin Lin Lin Liu Wang Chen