Locke Lord LLP
Control circuit, sampling circuit for synchronous dynamic random-access memory, method of reading procedure and calibration thereof
The present disclosure provides a memory control circuit configured to precede a data-reading process with a memory. For the data-reading process, the memory transmits a DQ and a DQS indicating a time to read the DQ. The DQS includes a preamble. The memory control circuit includes a control circuit and a sampling circuit. The control circuit is configured to generate an enabling signal. The sampling circuit coupled to the control circuit is configured to sample the DQS based on the enabling signal in order to determine a sampling level. The control circuit determines whether the sampling level matches a signal level of the preamble or not.
REALTEK SEMICONDUCTOR CORPORATION
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Shen-Kuo Chun-Chi Gerchih Chih-Wei
Huang Yu Chou Chang