Oliff & Berridge, PLC
Layered chip package with wiring on the side surfaces
A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include at least one specific pair of layer portions including a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. A layered substructure formed of a stack of two substructures, each of which includes aligned preliminary layer portions, is used to fabricate a stack of a predetermined two or greater number of pairs of layer portions, and the main body is fabricated by stacking an additional first-type layer portion together with the stack, the number of the additional first-type layer portion being equal to the number of the specific pair(s) of layer portions included in the stack.
SAE Magnetics (H.K.) Ltd. TDK Corporation Headway Technologies, Inc.
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Hiroyuki Yoshitaka Nobuyuki Hiroshi Satoru Tatsuya
Ito Sasaki Okuzawa Ikejima Sueki Harada