Slater & Matsil, L.L.P.
Parity look-ahead scheme for tag cache memory
A device includes a tag cache memory array; a pre-parity unit configured to receive an address, and calculate and output a pre-parity bit calculated from all bits of the address. A comparator is configured to compare a tag read from the tag cache memory array with the address, and output a read-hit bit. The read-hit bit is true when the tag and the address are identical, and is false when the tag and the address are not identical. The device further includes a simplified parity-check unit configured to receive and perform operations on the pre-parity bit, the read-hit bit, and a parity bit from the tag cache memory array, and to output a read-parity bit.
Taiwan Semiconductor Manufacturing Company, Ltd.
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G06F G06F H03M
inventional inventional inventional
Chi-Lin Chung-Cheng Yi-Tzu
Liu Chou Chen