Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cells
A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of via opens, and the second DOE contains fill cells configured to enable NC detection of metal island opens. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.
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Andrzej Kimon Indranil Nobuharu Carl Hans Stephen Dennis Timothy Marci Christopher Jeremy Marcin Rakesh Sherry Conor Markus Hideki Kelvin Sheng-Che John Larg Jonathan Vyacheslav Tomasz Simone
Strojwas Michaels De Yokoyama Taylor Eisenmann Lam Ciplickas Fiscus Liao Hess Cheng Strojwas Vallishayee Lee O'Sullivan Rauscher Matsuhashi Doong Lin Kibarian Weiland Haigh Rovner Brozek Comensoli