Haynes and Boone, LLP
Method of fabricating an integrated circuit with non-printable dummy features
The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r0 to optimize an uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for non-printable dummy features and adding the non-printable dummy features in the IC design layout.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Cheng-Hung Pei-Yi Burn Jeng Wen-Chuan Jyuh-Fuh Shy-Jay
Chen Liu Lin Wang Lin Lin