Flynn & Frishauf
Logic circuit arrangements using insulated-gate field effect transistors
 A clock pulse-controlled logic circuit arrangement wherein the source-drain path of a first transistor having its gate electrode supplied with a clock pulse and the source-drain paths of at least two second transistors jointly constituting a logic gate by having the respective gate electrodes supplied with data input are connected in series between a first and a second operating voltage supply point. To the junction of the first transistor and logic gate or an output point is connected an operation stabilizing circuit for replenishing the output point with a voltage signal having the same polarity as the output voltage signal to prevent any change in the level of the output voltage signal while the first transistor is rendered nonconducting. 
Tokyo Shibaura Electric Co., Ltd.
H
H03K
inventional
Yasoji
Suzuki