Finnegan, Henderson, Farabow, Garrett and Dunner
Nonvolatile semiconductor memory device with a double gate structure
 A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer. 
Kabushiki Kaisha Toshiba
G G
G11C G11C
inventional inventional
Kazuyoshi Ichiro Isao Tadashi Tomohisa Hiroyoshi Osamu Yasoji
Shinada Kobayashi Abe Maruyama Shigematsu Murata Matsumoto Suzuki