Fletcher Yoder, P.C.
Delay-locked loop clock sharing
An apparatus includes a memory device interface comprising a first data output, a second data output, a third data output, and a fourth data output, as well as a first path corresponding to the first data output, a second path corresponding to the second data output, a third path corresponding to the third data output, and a fourth path corresponding to the fourth data output. The apparatus also includes a signal transmission circuit comprising a first output that when in operation transmits a first clock signal to the first path, the second path, the third path, and the fourth path and a second output that when in operation transmits a second clock signal to the first path, the second path, the third path, and the fourth path.
Micron Technology, Inc.
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Younghoon Michael V.
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