K & L Gates LLP
Method for designing phase-lock loop circuits
A method for designing a phase-lock loop (PLL) circuit is disclosed. The method includes the following steps. A first set of intellectual properties, each of which represents a control circuit implemented on a semiconductor substrate, is provided. A second set of intellectual properties, each of which represents a filter implemented on the semiconductor substrate, is provided. Intellectual properties are selected from the first and second sets based on a predetermined specification of the PLL circuit. The selected intellectual properties are integrated as an integrated intellectual property representing the PLL circuit, such that a layout area of the PLL circuit implemented by using the integrated intellectual property is configured based on the predetermined specification.
Taiwan Semiconductor Manufacturing Co., Ltd.
H
H03L
inventional
Chih-Chiang Chien-Hung Mu-Jen
Chang Chen Huang