J. C. Patents
Phase lock loop (PLL) clock generator with programmable skew and frequency
A phase lock loop (PLL) clock generator with programmable frequency and skew is provided in the present invention, in which frequency of clock signals generated can be dynamically changed and skew of the clock signals generated can be dynamically adjusted by a computer program. Also, the signal skew due to the change of loading can be compensated. Therefore, the PLL clock generator based on a closed-loop configuration can better control the skew of clock signals to provide higher stability and durability to the system.
Via Technologies, Inc.
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inventional inventional inventional inventional
Hsin-Chieh You-Ming Jiin Wei-Yu Jyhfong
Lin Chiu Lai Wang Lin