Sughrue, Mion, Zinn, Macpeak & Seas, PLLC
Method for performing simulation of a semiconductor integrated circuit using a relative variation model
 A method for performing simulation of a semiconductor integrated circuit is disclosed in which a circuit simulation result taking into consideration can be obtained relative variation. In the method, possible maximum and minimum values of an element parameter, i.e., element parameters of a worst case taking into consideration the relative variation is determined from prescribed absolute and relative variation ranges to form a variation model. Based on the variation model, worst-case simulation is carried out taking into account the relative variation. 
NEC Corporation
G
G06F
inventional
Kyou
Suzuki