Kowert Hood Munyon Rankin and Goetzel PC
Hybrid asynchronous gray counter with non-gray zone detector for high performance phase-locked loops
Systems, apparatuses, and methods for implementing a hybrid asynchronous gray counter with a non-gray zone detector are described. A circuit includes an asynchronous gray counter coupled to control logic. The control logic programs the asynchronous gray counter to operate in different modes to perform various functions associated with a high-performance phase-locked loop (PLL). In a first mode, the asynchronous gray counter serves as a frequency detector to count oscillator cycles within a reference clock cycle. In a second mode, the asynchronous gray counter serves as a coarse phase detector to detect a phase error between a feedback clock and a reference clock. In a third mode, the asynchronous gray counter serves as a multi-modulus divider to divide an oscillator clock down to create a feedback clock. Using a single asynchronous gray counter for three separate functions reduces power consumption and area utilization.
Apple Inc.
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Dennis M. Yu Meei-Ling Samed Shaobo Dabin
Fischette, Jr. Chen Chiang Maltabas Liu Zhang