Meltzer, Lippe, Goldstein, et. al.
Variable length coding system having a zig-zag memory
 A variable length coder is disclosed having a zig-zag memory for continuously receiving blocks of coefficients while outputting the coefficients in zig-zag scan order. The zig-zag memory has a first memory for writing each odd ordinalled block therein according to a zig-zag scan as the odd ordinalled block is inputted. The first memory subsequently reads-out each of the zig-zag scanned odd ordinalled blocks while the zig-zag memory receives each even ordinalled block. The zig-zag memory also has a second memory for writing each even ordinalled block therein according to a zig-zag scan as the even ordinalled block is inputted. The second memory subsequently reads-out each of the zig-zag scanned ordinalled blocks while the zig-zag memory receives each odd ordinalled block. The zig-zag memory further includes a read counter which generates addresses and selectively outputs the addresses to the first memory for reading out each odd ordinalled block, while the zig-zag memory receives an even ordinalled block. The read counter similarly reads out each even ordinalled block, while the zig-zag memory receives an odd ordinalled block. The zig-zag memory additionally has a circuit, responsive to the generated addresses, for outputting a signal indicating whether or not the block coefficient currently read out of the zig-zag memory is a DC coefficient of the block. 
Industrial Technology Research Institute
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inventional inventional additional additional inventional inventional
Yueh-Chang
Chen