Myers Bigel Sibley & Sajovec
LCD panels including interconnected test thin film transistors and methods of gross testing LCD panels
Test thin film transistors are provided outside of the pixel region of an LCD panel that includes an array of pixel thin film transistors and intersecting arrays of spaced apart data lines and gate lines connected to the array of pixel thin film transistors. A respective test thin film transistor is connected to a respective one of the data lines or gate lines. At least subgroups of the test thin film transistors are commonly connected to provide common energization of subgroups of data lines or test lines for gross testing of the LCD panels. Rubber pads are therefore not required to energize each individual data line or gate line for gross testing. Moreover, after testing is completed, test thin film transistors need not be cut or otherwise mechanically disconnected. Test thin film transistors may be organized for tape automated bonding (TAB) LCD panels or for chip on glass (COG) LCD panels. Associated methods are also provided.
Samsung Electronics Co., Ltd.
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inventional inventional additional
Seog-chae
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