Finnegan, Henderson, Farabow, Garrett, & Dunner
Nonvolatile floating gate semiconductor memory device
 A nonvolatile semiconductor memory device comprises a cell transistor formed of a floating gate type MOS transistor, for storing an electric charge, whose gate is connected to a control gate line layer, a first selecting transistor formed of an MOS transistor, whose gate is connected to a read gate line layer, whose source-drain path is connected at one end to a read line layer, and at the other end to one terminal of the source-drain path of the cell transistor, and a second selecting transistor formed of an MOS transistor, whose gate is connected to a write gate line layer, whose source-drain path is connected at one end to a write line layer, and at the other end to the other terminal of the source-drain path of a cell transistor. A power source voltage of 5 V can be supplied to the read line layer in the read mode. 
Kabushiki Kaisha Toshiba
G H
G11C H01L
inventional inventional
Yukio Makoto Tomohisa Yasoji Tadashi
Wada Yoshizawa Shigematsu Suzuki Maruyama