JCIPRNET
Memory storage apparatus and method for testing memory storage apparatus
A memory storage apparatus including a memory cell array and a memory control circuit is provided. The memory cell array includes a plurality of memory cells. The memory cell array is configured to store data. The memory control circuit is coupled to the memory cell array. The memory control circuit is configured to apply one of a set signal and a reset signal to a target memory cell among the memory cells to generate a read current. The memory control circuit receives a read current of the target memory cell. The memory control circuit compares the read current with a reference current. The memory control circuit determines whether the target memory cell is failed according to a comparison result. In addition, a method for testing a memory storage apparatus is also provided.
Winbond Electronics Corp.
G G
G11C G11C
inventional additional
Bo-Lun Chia-Hua Meng-Hung Chuan-Sheng
Wu Ho Lin Chou