McDermott Will & Emery LLP
Memory cells breakdown protection
A method is disclosed that includes the operations outlined below. A first voltage is applied to a gate of an access transistor of each of a row of memory cells during a reset operation, wherein a first source/drain of the access transistor is electrically connected to a first electrode of a resistive random access memory (RRAM) device in the same memory cell. An inhibition voltage is applied to a second electrode of the RRAM device or to a second source/drain of the access transistor of each of a plurality of unselected memory cells when the first voltage is applied to the gate of the access transistor.
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
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Yu-Wen Sheng-Hung Wen-Ting Kuo-Chi Wen-Chun Chih-Yang Hsia-Wei Chin-Chieh
Liao Shih Chu Tu You Chang Chen Yang