Foley & Lardner
Cache access system for multiple requestors providing independent access to the cache arrays
 The present invention is an apparatus comprising first and second addressable arrays and an input for receiving address information related to the arrays. A first request line receives from a first source first request signals for access to the first and second arrays based on the address information. A second request line receives from a second source second request signals for access to the first and second arrays based on the address information. A processing circuit transmits the address information to the first and second addressable arrays in response to the first and second request signals based on a priority of the first and second request signals. 
Advanced Micro Devices, Inc.
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additional inventional inventional
Thang M.
Tran