Dickinson Wright PLLC
Multi BLCS for multi-state verify and multi-level QPW
An apparatus and method for a multi-state verify of a memory array are provided. A sense circuit of a memory device is connected to a bit line of the memory array. The sense circuit includes a first voltage clamp, a second voltage clamp, and a program data latch disposed on the bit line. The first and second voltage clamps are biased to first and second voltages, respectively, where the first voltage is lower than the second voltage. When a high bias is applied to the program data latch, the program data latch is in an OFF state, and the first voltage clamp limits the bias on the bit line to the first voltage. When a low bias is applied to the program data latch, the program data latch is in an ON state, and the second voltage clamp limits the bias on the bit line to the second voltage.
SanDiskTechnologies LLC
G G G G G G G G G
G11C G11C G11C G11C G11C G11C G11C G11C G11C
additional inventional inventional inventional inventional inventional inventional inventional inventional
Kou Jongyeon Ohwon Chia-Kai Hiroki
Tei Kim Kwon Chou Yabe