Thomas, Kayden, Horstemeyer & Risley
Dual damascene process
A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is spin coated to fill the via holes. Next, a layer of photoresist is applied. The photoresist is then exposed through a mask and developed to form an etch opening. Using the remaining photoresist as an etch mask and with a bottom anti-reflection coating (BARC) as protection, the oxide or low k layer is etched to form subsequent wiring. The etch step is known as a damascene etch step. The remaining photoresist is removed and the trench/via openings are filled with metal forming inlaid metal interconnect wiring and contact vias.
Taiwan Semiconductor Manufacturing Co., Ltd.
H
H01L
inventional
Hua-Tai Bang-Chien Jian-Hong Li-Te Li-Chih Tsang-Jiuh Shyue-Sheng
Lin Ho Chen Lin Chao Wu Lu