Asymmetric electro-static discharge transistors for increased electro-static discharge hardness
 An asymmetric electro-static discharge transistor includes a gate region formed on a substrate. The gate region includes a polysilicon gate region placed over a dielectric layer. A drain region is placed within the substrate. The drain region includes a first drain region implanted with atoms of a first conductivity type at a first concentration. The first drain region extends under the gate region. For example, the first drain region is a lightly doped n.sup.- region. A second drain region is formed adjacent to the first doped portion. The second drain region is implanted with atoms of the first conductivity type. For example, the second drain region is a heavily doped n.sup.+ region. A source region is formed within the substrate. The source region extends under the gate region. The source region is implanted with atoms of the first conductivity type. For example, the source region is a heavily doped n.sup.+ region. 
VLSI Technology, Inc.
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H01L H01L
inventional inventional
Tiao-Yuan
Huang