Adaptive instruction prefetching and fetching memory system apparatus and method for microprocessor system
A method and system of the instruction packing and scaling are designed for simultaneously enhancing energy efficiency by concurrent and advanced prefetching/fetching instructions via the small and/or banked caches and for improving the performance of microprocessors by reducing the fraction of program and by employing the simple and fast caches. The invention is also designed for converting high fraction code to simplified, branch-reduced, and hidden code during compilation time, for storing packed/scaled code to concurrently accessible the plurality of caches and main memories, and for reverting the code to the native instructions during the instruction prefetch and fetch operations. Consequently, the invention does not forward many flow control instructions including procedure callers/returns and unconditional branches to microprocessors. In particular, the invention accurately prefetches/fetches instructions from the main memories to small, simple, and fast caches, which significantly reduce leakage and dynamic power dissipation, access time, and chip area.
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additional inventional inventional
Yong-Kyu
Jung