Eschweiler & Potashnik, LLC
Extra doped region for back-side deep trench isolation
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensing element disposed within a semiconductor substrate. One or more isolation structures are arranged within one or more trenches disposed along a first surface of the semiconductor substrate. The one or more isolation structures are separated from opposing sides of the image sensing element by non-zero distances. The one or more trenches are defined by sidewalls and a horizontally extending surface of the semiconductor substrate. A doped region is laterally arranged between the sidewalls of the semiconductor substrate defining the one or more trenches and is vertically arranged between the image sensing element and the first surface of the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Yu-Jen Ching-Chun Dun-Nian Yen-Ting Tzu-Jui Jhy-Jyi Hsiao-Hui Yuichiro Shyh-Fann Chun-Yuan
Wang Wang Yaung Chiang Wang Sze Tseng Yamashita Ting Chen