Duane Morris LLP
Retention flip-flop
A master-slave retention flip-flop includes a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal, a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal, and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal.
Taiwan Semiconductor Manufacturing Co., Ltd.
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Shyh-An Yun-Han Shiue Tsong Jyy Anne
Chi Lee Shen Lee