Otterstedt, Wallace & Kammer, LLP
FinFET-based integrated circuits with reduced parasitic capacitance
An integrated circuit includes a first set of fins, a second set of fins, a gate, and a dielectric plug. The second set of fins is discrete from the first set of fins, and the gate passes over the first set of fins and the second set of fins. The dielectric plug is surrounded by the gate on two sides where the gate passes between the first set of fins and the second set of fins. Incorporation of aspects of the invention into integrated circuits with fin-based field effect transistors (FinFETs) helps to reduce parasitic capacitance between gate features and other nearby electrically conductive features.
International Business Machines Corporation
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Kangguo Juntao Chanro Ruilong
Cheng Li Park Xie