Seed IP Law Group LLP
Gate clock generator and display device having the same
The present disclosure provides a gate clock generator including a counter, a buffer control signal generator, and an output unit. The counter receives control data having rising timing information and falling timing information and a main clock. The counter generates a first output when a value is obtained by counting the main clock from a preset reference time point reaches rising data. The counter further generates a second output when a value is obtained by counting the main clock from the reference time point reaches falling data. The buffer control signal generator generates a first buffer control signal of a gate ON voltage from a timing of the first output to a timing of the second output. The output unit outputs a gate ON voltage of a gate clock during an output period of the gate ON voltage of the first buffer control signal.
LG DISPLAY CO., LTD.
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Jungjae Sanguk Jaewon Soondong Hyungjin
Kim Lee Han Cho Choe