Haynes and Boone, LLP
Method of fabricating an integrated circuit with block dummy for optimized pattern density uniformity
The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a plurality of main features; choosing isolation distances to the IC design layout; oversizing the main features according to each of the isolation distances; generating a space block layer for the each of the isolation distances by a Boolean operation according to oversized main features; choosing an optimized space block layer and an optimized block dummy density ratio of the IC design layout according to pattern density variation; generating dummy features in the optimized space block layer according to the optimized block dummy density ratio; and forming a tape-out data of the IC design layout including the main features and the dummy features, for IC fabrication.
Taiwan Semiconductor Manufacturing Company, Ltd.
G G G H G Y G
G06F G03F G06F H01L G06F Y02P G06F
inventional additional inventional additional additional additional inventional
Pei-Yi Jyuh-Fuh Cheng-Hung Wen-Chuan Burn Jeng Shy-Jay
Liu Lin Chen Wang Lin Lin