Haynes and Boone, LLP
Memory circuit and cache circuit configuration
A cache memory die includes a substrate, a predetermined number of sets of memory cells on the substrate, a first set of input/output terminals on a first surface of the cache memory die, and a second set of input/output terminals on a second surface of the cache memory die. The first set of input/output terminals are connected to a primary memory circuit outside the cache memory die. A portion of the second set of input/output terminals are compatible with the first set of input/output terminals.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
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William Wu Yun-Han Hsien-Hsin Sean
Shen Lee Lee