William Park & Associates Ltd.
Memory systems having a plurality of memory devices and methods of training the memory systems
A memory system includes a representative memory device directly outputting a representative data strobe signal, at least one non-representative memory device outputting a non-representative data strobe signal through the representative memory device, and a controller generating an internal delay clock signal synchronized with the representative data strobe signal. The controller outputs a test mode code defining a delay time using the internal delay clock signal as a reference signal. The at least one non-representative memory device adjusts a phase of the non-representative data strobe signal such that the non-representative data strobe signal has a delay time corresponding to the test mode code.
SK hynix Inc.
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Byung Deuk Yun Tack Kyu Tae Seong Ju
Jeon Han Park Lee