Eschweiler & Potashnik, LLC
Trim wall protection method for multi-wafer stacking
The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Cheng-Yuan Sheng-Chan Cheng-Hsien Sheng-Chau Kuo-Ming
Tsai Li Chou Chen Wu