Marger Johnson & McCollom, P.C.
Method for making shallow trench isolation in semiconductor fabrication
A method for making the Shallow Trench Isolation (STI) of a semiconductor device. An active mask layer is formed on a semiconductor substrate. Then the active mask layer and semiconductor substrate are etched to form a plurality of trenches. Next, an oxide layer is deposited by High Density Plasma Chemical Vapor Deposition (HDP-CVD) over the active mask layer so as to fill the trenches to a thickness greater than the depth of the trenches and less than the sum of the depth and the thickness of the active mask layer. A capping oxide layer is formed over the HDP-CVD oxide layer by means of plasma source of Tetra-Ethyl-Ortho-Silicate (TEOS). Subsequently, the capping oxide layer and HDP-CVD oxide layer are polished so as to expose the active mask layer. Thus, the Idoff characteristics of the transistor and thus the refresh characteristics of DRAM can be improved. Further, in another embodiment of the present invention, the HDP-CVD oxide layer partially fills the trenches, reducing the aspect ratio of the trenches. As a result, subsequent ozone-TEOS USG layer can completely fill the trenches without the formation of voids.
Samsung Electronics Co, Ltd.
H
H01L
inventional
Soo-Seun Hoon Seung-Jae
Lee Lim Lee