JCIPRNET
Mask assembly and method for fabricating a chip package
A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.
Taiwan Semiconductor Manufacturing Co., Ltd.
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Tzuan-Horng Hsien-Wei Ying-Ju Jie
Liu Chen Chen Chen