Mills & Onello LLP
Delay lock loop circuit
A delay lock loop circuit includes a reference loop for receiving an external clock signal and for generating a second output signal and a first output signal which includes a plurality of signals having different respective phases. A fine loop receives the external clock signal and the first output signal of the reference loop and generates an internal clock signal. A transition detecting circuit receives the second output signal of the reference loop and generates a protection signal by detecting a transition of the logic state of the second output signal of the reference loop. In response to the protection signal, the delay lock loop circuit in accordance with the present invention protects itself from an external clock signal that has a frequency that is out of the range of operable frequencies of the delay lock loop circuit, for example by disabling the entire circuit, or a portion of the circuit.
Samsung Electronics Co., Ltd.
H H
H03L H03L
inventional inventional
Jung-Hwan
Choi