Haynes and Boone, LLP
Method and system for reducing critical dimension side-to-side tilting error
A method for reducing a critical dimension error of a substrate is provided. A first function is identified for correlating a critical dimension error with a first effect. A second function is identified for correlating a critical dimension error with a scan speed. An optimal scan speed for minimizing the critical dimension error is identified by substantially equating the first function and the second function. The substrate may be a mask or a wafer.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Chai-Wei Cheng-Ming
Chang Lin