Blakely, Sokoloff, Taylor & Zafman LLP
Cache memory architecture with on-chip tag array and off-chip data array
 The present invention provides an improved cache memory architecture with way prediction. The improved architecture entails placing the address tag array of a cache memory on the central processing unit core (i.e. the microprocessor chip), while the cache data array remains off the microprocessor chip. In addition, a way predictor is provided in conjunction with the improved memory cache architecture to increase the overall performance of the cache memory system. 
Intel Corporation
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additional additional inventional inventional
Harsh Tim W. Gunjeet D. Cheng-Feng
Kumar Chan Baweja Chang