Jianq Chyun IP Office
Thin fan-out multi-chip stacked package structure and manufacturing method thereof
A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer is disposed on the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the dummy spacer are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and the surface of the dummy spacer but exposes the polished cross-sectional surfaces. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires.
Powertech Technology Inc.
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additional additional additional additional additional additional additional additional additional additional additional inventional inventional additional inventional additional additional additional additional additional additional inventional inventional inventional additional inventional inventional additional additional additional inventional
Chia-Wei Yong-Cheng
Chang Chuang