Cantor Colburn LLP
Vertical FET symmetric and asymmetric source/drain formation
A method for forming features of a vertical FET device, starting with a semiconductor substrate that includes fins and a horizontal surface. The fins also have a base, a top, and sidewalls. An etch process is performed to create bottom lateral recesses at the base of the fins. The method continues with growing a bottom source/drain region in the bottom recesses which forms PN junctions, and etching the fins to form top lateral recesses at the top of the fins. The method continues with growing a top source/drain region in the top recesses of the fins, therefore forming PN junctions.
INTERNATIONAL BUSINESS MACHINES CORPORATION
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Peng Zhenxing Juntao Kangguo
Xu Bi Li Cheng