IP & T Group LLP
Memory device and controlling method thereof
The present disclosure relates to a memory device may include a plurality of memory cells coupled to a selected word line and to be programmed to one of first to n-th program states distinguished from each other based on threshold voltages thereof, a sensing latch storing data sensed from a bit line coupled to one memory cell, a pre-latch storing pre-verify information and a plurality of data latches storing data to be stored in the one memory cell, wherein at least one data latch stores main verify information on the main verify voltage during verify operations for the first program state to a threshold program state among the first to n-th program states until the verify operation for the threshold program state passes, and wherein the pre-latch stores the main verify information on the n-th program state after the verify operation for the threshold program state passes.
SK hynix Inc.
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Hyung Jin
Choi