Kim & Stewart LLP
Semiconductor memory device and memory system
A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.
TOSHIBA MEMORY CORPORATION
G G G G G G G G
G06F G11C G06F G11C G11C G06F G11C G11C
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Weihan Noboru Toshifumi
Wang Shibata Hashimoto