JCIPRNET
Semiconductor structure having an anti-arcing pattern disposed on a passivation layer and method of fabricating the semiconductor structure
A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Ching-Jung Jie Hsien-Wei Ming-Fa Sheng-An
Yang Chen Chen Chen Kuo