Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
A process for making an integrated circuit, either in the form of a wafer, die, or chip, includes instantiating multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such instantiated fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such instantiated fill cells further include geometry to enable non-contact evaluation of Tip-to-Side shorts and/or leakages.
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Strojwas Hess Lin Vallishayee Cheng Haigh Taylor Doong Brozek Kibarian Lam Rovner De Eisenmann Lee O'Sullivan Rauscher Weiland Ciplickas Strojwas Michaels Yokoyama Comensoli Liao Matsuhashi Fiscus