Lowe Hauptman & Ham, LLP
Memory error correction
A method includes, by a first circuit, converting a plurality of bits in a first format to a second format. The plurality of bits in the second format is used, by a second circuit, to program a plurality of memory cells corresponding to the plurality of bits. The first format is a parallel format. The second format is a serial format. The first circuit and the second circuit are electrically coupled together in a chip. In some embodiments, the plurality of bits includes address information, cell data information, and program information of a memory cell that has an error. In some embodiments, the plurality of bits includes word data information of a word and error code and correction information corresponding to the word data information of the word.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
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Sung-Chieh Kuoyuan (Peter) Yun-Han
Lin Hsu Chen