Method of operating a memory device having write latency
 A method of operation of a memory device. The memory device including a section of memory having a plurality of memory cells. The method of operation comprises receiving a request for a write operation and sampling a first portion of data after a delay time transpires in response to the request for a write operation. A method of controlling the memory device comprises issuing a request for a write operation to the memory device. The memory device samples data after a number of clock cycles of the external clock signal transpire in response to the request. The method of controlling also comprises issuing a first portion of data to the memory device after the number of clock cycles of the external clock signal transpire. 
Rambus Inc.
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Mark Michael
Horowitz Farmwald