Jiang Chyun IP Office
Process for fabricating wafer bumps
A wafer bump fabrication process is provided in the present invention. A wafer with multiple bonding pads and a passivation layer, which exposes the bonding pads, is provided. The surface of each bonding pad has an under bump metallurgy layer. A patterned photoresist layer with a plurality of opening is formed which openings expose the under bump metallurgy layer. Afterwards a curing process is performed to cure the patterned photoresist layer. Following a solder paste fill-in process is performed to fill a solder paste into the openings. A reflow process is performed to form bumps from the solder paste in the openings. The patterned photoresist layer is removed.
Advanced Semiconductor Engineering, Inc.
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Chun-Chi Su Chao-Fu Yung-Chi Min-Lung Ching-Huei Jen-Kuang Yu-Chen Tsung-Hua Ho-Ming Jau-Shoung
Lee Tao Weng Lee Huang Su Fang Chou Wu Tong Chen