Enhanced ZDB feedback methodology utilizing binary weighted techniques
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a plurality of output clock signals in response to a reference clock signal and a feedback signal. The second circuit may be configured to select one of the plurality of output clock signals as the feedback signal in response to a first control signal. The first control signal may be configured to minimize a difference in delay between the plurality of output clock signals.
Cypress Semiconductor Corp.
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H03L H03L G06F
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David Daigo
Green Katagiri