Method for forming trench isolation
The semiconductor device has a trench isolation between a P-well and N-well. This trench isolation region is formed of oxide which during the course of the formation of the P and N well is doped with P-type and N-type dopants. Thus the trench has a P-type doped region and an N-type doped region which are typically phosphorous and boron. After the P and N well are formed, a rapid thermal anneal is applied to the device structure. This has the effect of causing the phosphorous doped and boron doped portions of the trench oxide to be etched at substantially the same rate. After this RTA step, gate oxide is formed over the P and N well. The following formation of polysilicon gates results in a relatively flat gate over transistor structure. This avoids corner leakage which is a problem with trench isolation.
Motorola, Inc.
H
H01L
inventional
Franklin D. Choh-Fei Jian
Nkansah Yeap Chen