Harness, Dickey & Pierce, P.L.C.
Test system for conducting parallel bit test
Provided is a test system conducting a parallel bit test. The test system, conducting a parallel bit test on a plurality of memory modules mounted on a socket, comprises a plurality of counters and a comparator. Each of the counters counts the number of data output signals in the same logic state, among the data output signals outputted from each memory of the memory modules, and outputs a count signal. The comparator compares the count signal outputted from each of the counters and outputs a comparison signal corresponding to a defect of the memory modules. According to the test system, defects in a memory module can be accurately detected and a possibility of an error in the detection can be reduced when a plurality of memory modules are tested, as compared to conventional test systems.
Samsung Electronics Co., Ltd.
G G G
G11C G11C G11C
inventional additional additional
Hee-joo Jung-kuk Seung-hee Byoung-sul
Choi Lee Lee Kim