Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines
 A sense amplifier is connected between memory cell arrays, a re-writing register is arranged in position adjacent to the sense amplifier, transfer gates are disposed between the sense amplifier and the memory cell arrays, transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines. 
Kabushiki Kaisha Toshiba
G G G G G G
G11C G11C G11C G11C G11C G11C
inventional inventional inventional inventional inventional inventional
Yukihito Shinichiro Ryu Shigeyoshi Fujio Takehiro
Oowaki Shiratake Ogiwara Watanabe Masuoka Hasegawa