Tracking status detector for a digital delay lock loop
 An unlocked detector for a digital delay lock loop employs an up-down cour which periodically accumulates the algebraic sum of the quantized positive and negative adjustments made at a preselected rate by the incremental phase modulator. Whenever this sum reaches a specified threshold value corresponding to a particular phase error, an unlocked indication is given. Arrangements utilizing the same principle are disclosed for analog loops. 
The United States of America as represented by the Secretary of the Navy
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H03K H03L Y10S
inventional inventional additional
James L. Chang Chung Jack K.
Lewis Chen Holmes