Myers Bigel Sibley & Sajovec, P.A.
Methods of operating memory devices including discharge of source/drain regions and related electronic devices
A memory device may include a memory cell array having a plurality of memory cell transistors serially coupled in a string between a string selection transistor and a ground selection transistor. The string selection transistor may be coupled between the string and a bit line, and the ground selection transistor may be coupled between the string and a common source line. In addition, each memory cell transistor may includes a floating gate between a control gate electrode and a semiconductor substrate, and source/drain regions of the semiconductor substrate may be included on opposite sides of the control gate electrode. Responsive to an erase command, the memory cell transistors of the string may be erased. Further responsive to the erase command and after erasing the memory cell transistors of the string, electrical charge from the source/drain regions of the memory cell transistors may be discharged through the ground selection transistor to the common source line and/or through the string selection transistor to the bit line. Related devices are also discussed.
Samsung Electronics Co., Ltd.
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G11C G11C
inventional inventional
Seungwon
Lee