Vierra Magen Marcus LLP
Multi-core lock-free rate limiting apparatus and method
An apparatus, such as a network element, comprises a receiver to receive a plurality of packets. A memory stores instructions and forms a first and second set of virtual queues to store the plurality of packets. A processor having one or more cores with one or more packet classifiers provides a classification of a packet in the plurality of packets. The processor in communication with the memory executes instructions to transfer the packet from the receiver to a virtual queue in the first set of virtual queues based on the classification. The processor also transfers the packet from the virtual queue to a transmitter based on a demand rate value and supply rate value associated with the virtual queue.
Futurewei Technologies, Inc.
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Jun Wei Yan Yizhen Zhe Xiaofeng Zhi
Li Xu Sun Liu Fu Yang Liu