William Park & Associates Patent Ltd.
Stack package and method for selecting chip in stack package
A stack package having a plurality of stacked chips includes first voltage dropping units respectively formed in the plurality of chips, the first voltage dropping units are electrically coupled by a first line; second voltage dropping units respectively formed in the plurality of chips, the second dropping units are electrically coupled by a second line; first signal generation units respectively formed in the plurality of chips, each of the first signal generation units is connected to an output node of the first voltage dropping units, respectively; and second signal generation units respectively formed in the plurality of chips, each of the second signal generation units is connected to an input node of the second voltage dropping units, respectively.
SK Hynix Inc.
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Dae Woong Byoung Do Chul Keun Tae Min Yu Hwan Jae Hyun Yu Gyeong
Lee Lee Yoon Kang Kim Son Hwang