Integrated circuit having memory which synchronously samples information with respect to external clock signals
 A synchronous memory device having at least one memory section which includes a plurality of memory cells. The memory device includes clock receiver circuitry, clock generation circuitry and input receiver circuitry. The clock receiver circuitry receives an external clock signal from an external bus. The clock generation circuitry is coupled to the clock receiver circuitry, and includes a delay locked loop to generate a first internal clock signal. The input receiver circuitry is coupled to the clock generation circuitry and the external bus to sample information from the external bus in response to the first internal clock signal. 
Rambus Inc.
G G G G G G G G G G G G G G G G Y G G G G G G G G G G G G G G G G G G G G
G06F G11C G06F G11C G11C G11C G11C G11C G06F G11C G06F G06F G11C G11C G11C G11C Y02D G11C G06F G06F G11C G11C G11C G11C G11C G11C G06F G11C G11C G06F G06F G06F G06F G11C G11C G11C G11C
inventional inventional additional inventional inventional inventional inventional additional inventional inventional inventional inventional inventional inventional inventional inventional additional inventional inventional inventional inventional inventional additional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional
Mark Michael
Horowitz Farmwald