Leading bit prediction with in-parallel correction
For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of adding or subtracting two floating point numbers. In one embodiment, the logic circuitry includes: (1) an adder that receives the two floating point numbers and, based on a received instruction, adds or subtracts the two floating point numbers to yield a denormal sum or difference thereof, (2) a leading bit predictor that receives the two floating point numbers and performs logic operations thereon to yield predictive shift data denoting an extent to which the denormal sum or difference is required to be shifted to normalize the denormal sum or difference, the predictive shift data subject to being erroneous and (3) predictor corrector logic that receives the two floating point numbers and performs logic operations thereon to yield shift compensation data denoting an extent to which the predictive shift is erroneous. The denormal sum or difference, predictive shift data and shift compensation data are providable to a shifter to allow the denormal sum or difference to be normalized.
National Semiconductor Corporation
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G06F G06F G06F
inventional inventional inventional
Atul Jeffrey A. Daniel W. Bang
Dhablania Lohman Green Nguyen