Schwabe, Williamson & Wyatt, P.C.
Contact techniques and configurations for reducing parasitic resistance in nanowire transistors
Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.
Intel Corporation
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Marko Ravi Matthew V. Han Wui Benjamin Gilbert Willy Niloy Van H.
Radosavljevic Pillarisetty Metz Then Chu-Kung Dewey Rachmady Mukherjee Le