Hauptman Ham, LLP
Method of generating a simulation model of a predefined fabrication process
A method of generating a simulation model of a predefined fabrication process according to a sample conductive feature includes receiving a geometry configuration and layout design of the conductive feature. A circuit-level simulation model of the sample conductive feature based on the geometry configuration of the sample conductive feature is generated. A hardware processor converts the circuit-level simulation model of the sample conductive feature into at least a first layout bias rule corresponding to a first set of predetermined criteria of the layout design and a second layout bias rule, different from the first layout bias rule, corresponding to a second set of predetermined criteria of the layout design.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
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Chia-Ming Hsiao-Shu Ke-Ying Yi-Kan
Ho Chao Su Cheng