McDermott, Will & Emery
Semiconductor memory device permitting time required for writing data to be reduced
 A precharge circuit and a bit line load circuit are provided to a read bit line pair. The bit line load circuit continuously supplies a prescribed current to a read bit line. When data is written to one of memory cells selected in common by one read word line, the level of each read bit line will not be lowered to the level of the ground potential by the bit line load circuit if a read word line is activated, and therefore the loads of both discharge and charge operations by transistors in the memory cell are reduced. 
Mitsubishi Denki Kabushiki Kaisha
G
G11C
inventional
Niichi Tetsuya Yasunobu Chikayoshi
Itoh Watanabe Nakase Morishima