MOS transistor having reduced source/drain extension sheet resistance
The present invention provides a novel MOS transistor structure. The MOS transistor includes a gate electrode formed on a semiconductor substrate, and a gate oxide layer formed between the gate electrode and the semiconductor substrate. A spacer is formed on each sidewall of the gate electrode. A lightly doped source/drain extension is formed under the spacer with a raised epitaxial layer interposed between the spacer and the semiconductor substrate. The epitaxial layer, which is part of the lightly doped source/drain extension, has a lattice constant that is greater than the lattice constant of silicon crystal. The epitaxial layer serves as a solubility enhancement layer that is capable of increasing active boron concentration, thereby reducing sheet resistance of the source/drain extension. A heavily doped source/drain region is formed in the semiconductor substrate next to the edge of the spacer. A raised silicide layer is formed on the heavily doped source/drain region.
United Microelectronics Corp.
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Chin-Cheng Hsiang-Ying Yu-Kun Neng-Hui
Chien Wang Chen Yang