Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
A process for making an integrated circuit, either in the form of a wafer, die, or chip, includes instantiating multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such instantiated fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such instantiated fill cells further include geometry to enable non-contact evaluation of interlayer overlap shorts and/or leakages.
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Hideki Timothy John Christopher Sherry Conor Tomasz Vyacheslav Rakesh Marcin Hans Dennis Kelvin Jeremy Kimon Larg Indranil Sheng-Che Andrzej Markus Simone Marci Stephen Carl Jonathan Nobuharu
Matsuhashi Fiscus Kibarian Hess Lee O'Sullivan Brozek Rovner Vallishayee Strojwas Eisenmann Ciplickas Doong Cheng Michaels Weiland De Lin Strojwas Rauscher Comensoli Liao Lam Taylor Haigh Yokoyama