Method for reduced load memory module
A method for reducing load in a memory module. In such a method, a plurality of memory chips are coupled to a circuit platform. Each memory chip of the plurality of memory chips each has a plurality of memory dies. At least one controller is coupled to the circuit platform and further coupled to the plurality of memory chips for communication with the plurality of memory dies thereof. The at least one controller is for receiving chip select signals to provide a plurality of rank select signals in excess of the chip select signals. The plurality of memory dies are coupled with wire bonds within the plurality of memory chips for a reduced load for coupling the circuit platform for communicating via a memory channel. The load is sufficiently reduced for having at least two instances of the memory module share the memory channel.
Invensas Corporation
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Zhuowen Yong
Sun Chen