Haynes and Boone, LLP
Method for dual damascene process
The present disclosure provides a method of dual damascene processing. The method includes providing a substrate having vias formed therein; forming an under-layer in the vias and on the substrate; applying a solvent washing process to the under-layer; forming a silicon contained layer on the under-layer; patterning the silicon contained layer (SCL) to form SCL openings exposing the under-layer within the SCL openings; and etching the substrate and the under-layer within the SCL openings to form trenches.
Taiwan Semiconductor Manufacturing Company, Ltd.
H H
H01L H01L
inventional inventional
Ching-Yu Jen-Chieh
Chang Shih