Eschweiler & Potashnik, LLC
Interconnect landing method for RRAM technology
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a memory device over a substrate and forming an inter-level dielectric (ILD) layer over the memory device. The ILD layer is selectively etched to define a first cavity that exposes a top of the memory device and to define a second cavity that is laterally separated from the first cavity by the ILD layer. The second cavity is defined by a smooth sidewall of the ILD layer that extends between upper and lower surfaces of the ILD layer. A conductive material is formed within the first cavity and the second cavity.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Wen-Ting Kuo-Chi Chih-Yang Chin-Chieh Hsia-Wei Yu-Wen Jen-Sheng
Chu Tu Chang Yang Chen Liao Yang