Patent Capital Group
Silicon PMOS with gallium nitride NMOS for voltage regulation
This disclosure pertains to a gallium nitride transistor that is formed in a trench etched into a silicon substrate. A gallium nitride layer is on the trench of the silicon substrate. A source electrode and a drain electrode reside on the gallium nitride layer. A gate electrode resides on the gallium nitride layer between the source electrode and the drain electrode. A first polarization layer resides on the gallium nitride layer between the source electrode and the gate electrode, and a second polarization layer resides on the gallium nitride layer between the gate electrode and the drain electrode. The silicon substrate can include a silicon 111 substrate.
Intel Corporation
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Sansaptak Marko Roza Han Wui Valluri R. Peter G.
Dasgupta Radosavljevic Kotlyar Then Rao Tolchinsky