F. Chau & Associates, LLC
Semiconductor memory system performing data error correction using flag cell array of buffer memory
A buffer memory includes a memory cell array, a flag cell array, and a error correction block. The memory cell array has a plurality of word lines. Each of the plurality of word lines are electrically connected to a plurality of memory cells storing data. The flag cell array has a plurality of flag cells. Each of the plurality of flag cells is connected to each of the word lines and stores information that indicates whether error correction of the data has been performed. The error correction block performs error correction on the data output from the memory cell array in response to a command received through a host interface and flag data output from the flag cell array.
Samsung Electronics Co., Ltd.
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Byeong Hoon Sun Kwon Ki Hong Seung Won
Lee Kim Kim Lee