Burns, Doane, Swecker & Mathis, LLP
Semiconductor memory device with reduce coupling capacitance
The semiconductor memory device comprising a plurality of memory cells aligned in a matrix form, and a plurality of bit lines respectively extending along the memory cells aligned in the longitudinal direction, wherein each of the bit lines is provided with a line section of the upper layer and that of the lower layer, and the mutually adjacent portions of the respectively adjacent two bit lines are provided in the different layers from each other. Due to this construction, such a conventional problem that the specific gravity of the coupling capacitance occupied within the whole bit-line capacitance is made large and an erroneous operation is caused due to this narrowed coupling capacitance can be solved.
Mitsubishi Denki Kabushiki Kaisha
G
G11C
inventional
Tadayoshi Tadao
Nakano Yamaguchi