Morgan, Lewis & Bockius LLP
Memory controller with circuitry to set memory device-specific reference voltages
An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
Rambus Inc.
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Benedict Chung-Kwong Stefanos Bruno W. Mark A. Kevin S. Leung Jun Jared LeVan Donald C. Tsyr-Chyang Roxanne
Lau Sidiropoulos Garlepp Horowitz Donnelly Yu Kim Zerbe Stark Ho Vu