Perkins Coie LLP
Semiconductor devices having electrostatic discharge layouts for reduced capacitance
Semiconductor devices having busing layouts configured to reduce on-die capacitance are disclosed herein. In one embodiment, a semiconductor device includes an electrostatic discharge device electrically connected in parallel with an integrated circuit and configured to divert high voltages generated during an electrostatic discharge event away from the integrated circuit. The semiconductor device further includes a signal bus and a power bus electrically connected to the electrostatic discharge device. The signal bus includes a plurality of first fingers grouped into first groups and the power bus includes a plurality of second fingers grouped into second groups. The first groups are positioned generally parallel to and interleaved between the second groups.
Micron Technology, Inc.
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Michael V. Eric J.
Ho Smith