Skjerven, Morrill, MacPherson, Franklin & Friel LLP
Clock network for field programmable gate array
 A clock network of a field programmable gate array has a first clock bus extending across the chip in a first dimension. A clock pad can be coupled to the first clock bus if the clock network is to be driven from the clock pad. An output of a selected logic cell can be coupled to the first clock bus if the clock network is to be driven from a logic cell. To increase speed of the clock network, the first clock bus is segmented (in one embodiment, collinearly extending segments can be selectively coupled together via selectively programmable antifuses) so that only a short piece of the first clock bus is used to couple either the pad or the logic cell to the clock network in high speed applications. 
QuickLogic Corporation
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H03K H03K
inventional inventional
David D. Mukesh T. Ker-Ching
Eaton Lulla Liu