Flash EEPROM cell and array with bifurcated floating gates
 Each unit cell (10) of a flash EEPROM array (50) includes a source (18), a drain (20) and a channel (22) formed in a substrate (12). A thin tunnel oxide layer (32) is formed over the substrate (12) and P-Well (14). A bifurcated floating gate (34) is formed on the tunnel oxide layer (32) overlying the channel (22) , and includes a program arm (34a) which overlaps the drain (20), an erase arm (34b) which overlaps the source (18) and a base (34c) which extends around an end of the channel (22) and interconnects the program and erase arms (34a,34b). A thick gate oxide layer (36,36a) is formed over the floating gate (34), and a control gate (38) is formed over the gate oxide layer (36,36a). A central section of the control gate (38) which overlies a gap (34d) between the program and erase arms (34a, 34b) provides threshold voltage control for erasure. The erase arm (34b) spans the entire width of the channel (22), enabling erasure with low applied voltages. The bifurcated floating gate design automatically compensates for alignment error during fabrication such that the relative areas of the channel (22) which underlie the program/erase arms (34a, 34b) and gap (34d) are independent of the location of the gap (34d). 
Hughes Aircraft Company
H H
H01L H01L
inventional inventional
Mei F. Chen-chi P. Joseph E.
Li Chang Farb