Shadow translation look-aside buffer and method of operation
 For use in an x86-compatible processor having a physically-addressable cache and a primary translation look-aside buffer (primary TLB) that translates logical addresses into physical addresses for addressing the cache, a circuit and method for increasing a translation speed of the primary TLB and a computer system employing the circuit or the method. In one embodiment, the circuit includes a shadow TLB, located proximate the cache, that contains a copy of physical addresses stored in the primary TLB, the physical addresses retrievable from the shadow TLB thereby avoiding logic circuitry interposed between the primary TLB and the cache. 
National Semiconductor Corporation
G
G06F
inventional
Daniel W.
Green