Blakely, Sokoloff, Taylor & Zafman LLP
Method and apparatus for staggering execution of a single packed data instruction using the same circuit
 A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand. 
Intel Corporation
G G G G G G
G06F G06F G06F G06F G06F G06F
inventional inventional inventional inventional inventional inventional
Brent R. Patrice Karol F. Glenn J. Shreekant S.
Boswell Roussel Menezes Hinton Thakkar