Hauptman Ham, LLP
Method of forming the gate electrode of field effect transistor
A method includes depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature. The method includes performing a first chemical mechanical planarization (CMP) to expose the gate. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H H H H H H H H H H H H H H H
H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L
additional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional additional inventional
Sey-Ping Chun-Wei Yi-An Neng-Kuo Clement Hsingjen
Sun Chang Lin Chen Wann