Integrated process sequence allowing elimination of polysilicon residue and silicon damage during the fabrication of a buried stack capacitor structure in a SRAM cell
A process sequence for fabricating a buried stack capacitor structure, to be used as a component in a memory cell such as a one transistor SRAM cell, has been developed. The process features formation of a self-aligned opening used to accommodate a subsequent buried stack capacitor structure, with the self-aligned opening defined via selective dry and wet etch procedures, employed to avoid damage to regions of a semiconductor substrate which become exposed at the conclusion of the definition procedure. In addition the process sequence allows a smooth, top surface topography to be present during definition of a polysilicon storage node structure in the self-aligned opening, allowing unwanted portions of polysilicon to be easily removed, reducing the risk of polysilicon stringers.
Taiwan Semiconductor Manufacturing Company
H H
H01L H01L
inventional inventional
Min-Hsiung Chung-Wei Kuo-Chyuan
Chiang Chang Tzeng