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ESD protection devices for SOI integrated circuit and manufacturing method thereof
The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness.
Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
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inventional inventional inventional
Xing Xinhong Miao Xiaolu Xi Jing
Wei Cheng Zhang Huang Wang Chen