Davis Wright Tremaine LLP
Charge cycling by equalizing and regulating the source, well, and bit line levels during write operations for NAND flash memory: program to verify transition
In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.
SanDisk Technologies Inc.
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inventional inventional additional
Sung-En Man Lung Jongmin Masahide Juan Carlos Hao Thai Seungpil
Wang Mui Park Matsumoto Lee Nguyen Lee