Townsend and Townsend
Chained addressing mode pipelined processor which merges separately decoded parts of a multiple operation instruction
 A data processor of the present invention adopts a multi-stage indirect (chained) addressing mode, and merges pipeline processing units which are generated with respect to each designation of the chained addressing mode into a pipeline processing unit expressing the operation information for the operand of the instruction after completion of address calculation, thereby processing loads at each stage are equalized and processing speed as a whole apparatus increases. 
Mitsubishi Denki Kabushiki Kaisha
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Tetsuya Toyohiko
Watanabe Yoshida