Unified placer infrastructure
Method and apparatus are described for a placer system for placing design objects onto an arrayed architecture, such as a programmable logic device including an FPGA. More particularly, a placer interface is described for communicating with a placer core. The placer interface receives information from external entities, and unifies and generalizes this information for the placer core. The external entities comprise different representations of architecture, design, device, constraints and algorithm-dictated placer-movable objects.
Xilinx, Inc.
G
G06F
inventional
Guenter Sudip K. James L. Krishnan Jason H.
Stenz Nag Saunders Anandh Anderson