McGinn IP Law Group, PLLC
Clock generator
A multiphase clock with high resolution is generated. A first clock generator circuit (120) includes n level converters BUFs that conduct level conversion on two input signals, and generate a pair of pulse signals that switch the levels with reference to a crossing point at which the two signal are identical in level with each other. An i-th BUF in the first clock generator circuit (120) inputs a one-side output pair that is respective one-side outputs of the differential outputs of two i-th (1≦i≦n) and (i+1)-th (1 when i=n) differential circuits in a ring oscillator 110 in which n differential circuits DCELs having differential inputs and outputs are connected in a ring configuration. The one-side output pair is two one-side outputs that are input to the noninverting terminal of the next differential circuit, or the two one-side outputs that are input to the inverting terminal of the next differential circuit.
NEC Electronics Corporation
G
G06F
inventional
Masaki
Sano