Memory device data latency circuits and methods
A memory device can include a data path that includes a first-in-first-out circuit (FIFO) to transfer data according to a latency between at least one memory cell array and signal connections of the memory device, the latency corresponding to a number of cycles of a periodic clock; and a self-timed section configured to transfer data independent of the clock. In addition or alternatively, a memory device can include at least one memory cell array; and a FIFO configured to transfer data between at least one memory cell array and other portions of the memory device according to a periodic clock signal, FIFO introducing a latency into the data according to a control signal generated in response to an access command. Methods corresponding to the above devices and operations are also disclosed.
Cypress Semiconductor Corporation
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Joseph Thinh
Tzou Tran