Eschweiler & Potashnik, LLC
Integration of multiple fin structures on a single substrate
Various embodiments of the present disclosure are directed towards an integrated chip (IC) including a first fin structure and a second fin structure vertically extending from a semiconductor substrate, respectively. The first fin structure laterally extends along a first direction and has a first width. The second fin structure laterally extends along the first direction and has a second width that is less than the first width. A first plurality of nanostructures directly overlies the first fin structure and is vertically spaced from the first fin structure by a non-zero distance. A gate electrode continuously laterally extends along a second direction that is substantially perpendicular to the first direction. The gate electrode directly overlies the first and second fin structures, and wraps around the nanostructures.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Chih-Chao Shi Ning Kuo-Cheng Chih-Hao Wen-Ting
Chou Ju Chiang Wang Lan