Electrically erasable programmable logic device
An electrically erasable programmable logic device includes a P-type substrate, a first N-type doped region located inside the P-type substrate, and a first gate located on the P-type substrate. The first gate is adjacent to the first N-type doped region, is in a floating state, and is used for storing data. A second N-type doped region is located inside the P-type substrate adjacent to the first gate. A second gate is located on the P-type substrate and adjacent to the second N-type doped region and acts as a select gate. A third N-type doped region is located inside the P-type substrate adjacent to the second gate.
eMemory Technology Inc.
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G11C G11C H01L H01L
inventional additional inventional inventional
Kung-Hong Ya-Chin Ming-Chiu Ching-Hsiang Shih-Jye
Lee King Ho Hsu Shen