Birch, Stewart, Kolasch & Birch, LLP
Power metal oxide semiconductor transistor layout with lower output resistance and high current limit
A power metal oxide semiconductor transistor layout is disclosed. The power metal oxide semiconductor transistor layout uses network of conductive lead line as a connection or a network connection to connect source and drain regions thereby achieves advantages of a high uniformity of current, low Rds_on, much less power loss, an actual line density two times larger than that of conventional layouts and a strengthened resistance to electron migration.
Richtek Technology Corp.
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Chung-Lung Jing-Meng Hung-Der Chun-Yen
Pai Liu Su Huang