McDermott Will & Emery LLP
Semiconductor device
A memory cell transistor and a trench capacitor are provided in a memory region, and both transistors of CMOS are provided in a logic circuit region. There are provided a bit line contact 31 and a bit line 32 extending on an inter-level dielectric 30. In a memory cell transistor, a source diffusion layer 18 is covered with two dielectric sidewalls 25a and 25b in the memory cell transistor so that no silicide layer is formed on the source diffusion layer 18. A plate contact 31 is provided to pass through the inter-level dielectric 30 and connect a shield line 33 to a plate electrode 16b. The shield line 33 is arranged in the same interconnect layer as the bit line 32. 
Matsushita Electric Industrial Co., Ltd.
H H Y H Y
H01L H01L Y10S H01L Y10S
inventional additional additional additional additional
Hisashi Takayuki Yoshihiro Koji Kazuichiro Isao
Ogawa Yamada Mori Eriguchi Itonaga Miyanaga