Amin, Turocy & Calvin, LLP
Optimizing critical dimension uniformity utilizing a resist bake plate simulator
A system for optimizing critical dimension uniformity in semiconductor manufacturing processes is provided. The system comprises a bake plate simulator to model a physical bake plate. A finite element analysis engine uses information from the bake plate simulator to calculate missing information. A lithography simulator predicts outcomes of a lithography process using information from the bake plate simulator and the finite element analysis engine. The system can be used in a predictive capacity or as part of a process control system.
Advanced Micro Devices, Inc.
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Joyce S. Oey Iraj Qiaolin Luigi Bhanwar
Hewett Emami Zhang Capodiece Singh