Jones Volentine, LLC
Semiconductor memory
 A semiconductor memory of wherein the delay of control signals for controlling sense amplifiers is efficiently controlled without extensively changing a currently-used fabricating process. A dummy bit line pair are arranged between desired bit line pairs in the memory cell array. Since the dummy bit line pair is not related to a normal operation such as reading data stored in memory cells, it is not necessary to dispose a sense amplifier in an area of a sense amplifier array adjacent to the dummy bit line pair. As a result, there is formed a free area in the sense amplifier array. The free area has at least a width between the dummy bit line pair. This free area further forms a contact portion for electrically connecting sense amplifier control signal lines and low resistance sense amplifier control signal lines. That is, this free area is utilized as a shunt area of the sense amplifier control signal lines. 
Oki Electric Industry Co., Ltd.
G H H G
G11C H01L H01L G11C
inventional inventional additional inventional
Hidekazu
Kikuchi