Antonelli, Terry, Stout & Kraus, LLP
Packet switching apparatus with a common buffer
A plurality of address chains are assigned to each of such flows as output lines, priority control, etc. in the address management carried out in a switch with a shared buffer. Each of the address chains has a write address register 20 and a read address register 30. The switch is also provided with a distributive pointer 22 for distributing cells in a flow to a plurality of address chains and a write address register selector 21, as well as a read pointer 32 for reading packets from a plurality of the address chains and a read address register selector 31 so as to read the packets through a pipeline with use of those plural address chains.
Hitachi, Ltd.
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Mitsuhiro Takahiko Norihiko Hiroaki
Wada Kozaki Moriwaki Kasahara