Slater Matsil, LLP
Method and apparatus for modeling multi-terminal MOS device for LVS and PDK
A method comprises identifying a semiconductor device layout region comprising a first n-type metal oxide semiconductor (MOS) device having a first pair of face-to-face diodes adjacent to a second n-type MOS device having a second pair of face-to-face diodes and adding a dummy device between a first body contact of the first n-type MOS device and a second body contact of the second MOS device.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Cheng-Te Chin-Yuan Yi-Kan Chih Ming Chau-Wen
Chang Huang Cheng Yang Wei