Heslin Rothenberg Farley and Mesiti PC
Method, system and program product for identifying anomalies in integrated circuit design layouts
Disclosed is a method and corresponding system and program product that includes providing integrated circuit design layout(s), deconstructing the integrated circuit design layout(s) into unit-level geometric constructs, identifying anomalies in the unit-level geometric constructs, and storing anomaly data in a database. The method further includes determining one or more feature attributes for each of the plurality of unit-level geometric constructs, annotating the unit-level geometric constructs with feature attributes, resulting in annotated unit-level geometric constructs, mapping the annotated unit-level geometric constructs in a hyperplane formed by one or more feature attributes, each of the one or more feature attributes forming a dimensional axis of the hyperplane, resulting in a mapped hyperplane, applying a first model to the mapped hyperplane, identifying the anomalies from applying the first model, and applying a second model to the mapped hyperplane to rank the anomalies for printability risk, the generated data including rank data.
GLOBALFOUNDRIES Inc.
Y G G G G
Y02P G03F G06F G06F G06F
additional inventional inventional additional additional
Uwe Paul Karthik Wei-Long Fadi S. Sriram Piyush Robert C.
Schroeder Krishnamoorthy Wang Batarseh Madhavan Pathak Pack