Ladas & Parry LLP
Multi-bit pipeline analog-to-digital converter having shared amplifier structure
A multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage and removing a sampling error of the input voltage; N-bit flash ADCs of first to K-th stages receiving analog signals, converting them into digital signals and outputting the digital signals; N-bit multiplying digital-to-analog converters (MDACs) of first to K-th stages converting differences between the digital signals output from the N-bit flash ADCs and output signals of preceding stages back into analog signals and outputting the analog signals; and a three-stage amplifier connected to an output of the N-bit MDAC of the first stage at a first clock and an output of the SHA at a second clock, wherein intergers N>= and K>=2. An amplifier can be shared between an SHA and an MDAC of a first stage, thereby reducing power consumption and chip size.In the multi-bit pipeline ADC, an amplifier can be shared between an SHA consuming much power and an MDAC of a first stage, so that power consumption and chip size can be reduced.
Electronics and Telecommunications Research Institute
H H
H03M H03M
additional inventional
Young Deuk Jong Kee Kwi Dong Jong Dae Seung Chul
Jeon Kwon Kim Kim Lee