SOI trench capacitor cell incorporating a low-leakage floating body array transistor
A DRAM array in an SOI wafer having a uniform BOX layer extending throughout the array eliminates the collar oxide step in processing; connects the buried plates with an implant that, in turn, is connected to a conductive plug extending through the device layer and the box that is biased at ground; while the pass transistors are planar NFETs having floating bodies that have a leakage discharge path to ground through a grounded bitline.
International Business Machines Corporation
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Brian L. Denise Michael D. David M. Karen A. Herbert L. Mahendar
Walsh Pendleton Steigerwalt Dobuzinsky Bard Ho Kumar