Ladas & Parry
Delay locked loop circuit with improved jitter performance
A delay locked loop circuit with a novel structure for improving a jitter performance is disclosed. The delay locked loop circuit includes a delay circuit for receiving an input clock signal and generating a delayed output clock signal. The delay circuit has a predetermined minimum variable delay, and the output clock signal is delayed with respect to the input clock signal by a delay to be determined in accordance with a delay control signal inputted into the delay circuit. Moreover, the delay locked loop circuit includes a phase determining block for receiving the input clock signal and the output clock signal, generating a phase pull signal when a phase of an input clock signal being delayed by a first predetermined time period leads a phase of the output clock signal, and generating a phase push signal when a phase of the input clock signal lags behind a phase of a delayed output clock signal delayed by a second predetermined time, and a delay control circuit for generating the delay control signal for controlling the delay circuit to reduce the delay when the phase pull signal is received from the phase determining block and to increase the delay when the phase push signal is received from the phase determining block. The delay control circuit does not change the delay of the delay circuit when neither the phase pull signal nor the phase push signal is received from the phase determining block.
Hynix Semiconductor Inc.
H H
H03L H03L
inventional inventional
Seong Hoon
Lee