Skjerven, Morrill, MacPherson, Franklin & Friel LLP
Parallel access micro-TLB to speed up address translation
 A memory management unit (MMU) includes a translation lookaside buffer capable of simultaneously servicing three requests supplied to the MMU by an instruction cache and two data caches, respectively. Also, an arbiter selects one of several pending requests from sources of different priorities for immediate processing by the MMU, using a process which avoids undue delay in servicing requests from sources of lower priority. 
Fujitsu Limited
G G
G06F G06F
additional inventional
Ming-Ying Kioumars Joel F. Chih-Wei David Jen-Hong Charles
Li Dawallu Boney Chang Chen