Rabin & Berdo, P.C.
Wafer structure with a multi-layer barrier in an UBM layer network device with power supply
A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation layer covers the active surface of the semiconductor substrate and exposes the bonding pads. The UBM layers are respectively arranged on the bonding pads, and each UBM layer includes an adhesive layer, a super-lattice barrier layer and a wetting layer. The adhesion layer is disposed on bonding pads. The super-lattice barrier layer is disposed on the adhesion layer and includes a number of alternately stacked sub-barrier layers and sub-wetting layers. The wetting layer is disposed on the super-lattice barrier layer, and the bump is disposed on the wetting layer.
Advanced Semiconductor Engineering Inc.
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Tsung-Chieh Tsung-Hua Li-Cheng Jiunn Shih-Kuang Jui-I Shyh-Ing Chueh-An
Ho Wu Tai Chen Chen Yu Wu Hsieh