Haynes and Boone, LLP
Multiple-grid exposure method
A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (Δt) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Y10S G03F B82Y G03F H01J B82Y G03F H01J
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Shy-Jay Pei-Yi Wen Chuan Jaw-Jung Burn Jeng
Lin Liu Wang Shin Lin