High speed FRAM including a deselect circuit
High speed FRAM including a deselect circuit is realized for replacing SRAM, wherein the deselect circuit is connected to a local bit line pair for forcing a middle voltage to storage nodes of ferroelectric capacitors of unselected memory cell while a plate line of the ferroelectric capacitors is forced to the middle voltage, so that the unselected memory cell is not polarized while selected memory cell is polarized by changing the local bit line pair when writing. With the deselect circuit, half of the memory cells are not accessed, which reduces number of sense amps. Furthermore, half of metal routing lines on the memory cells can be used for selecting columns and connecting global power as the convention SRAM configuration, while other half of metal routing lines are used for global bit lines. And various circuits for implementing the memory with the deselect circuit are described.
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inventional inventional
Juhan
Kim