Memory system having memory devices each including a programmable internal register
 A memory system having a plurality of memory devices, each having at least one memory array which includes a plurality of memory cells. The memory system comprises a bus, a controller, a first memory device, and a second memory device. The bus includes a plurality of sisal lines coupled to the plurality of memory devices. The bus provides a transaction request including identification information generated by the controller, to the plurality of memory devices. The first and second memory device each include a programmable register, interface circuitry, and comparison circuitry. The interface circuitry of each memory device may store a memory identification value to identify each memory device on the bus. The interface circuitry of each memory device is coupled to the bus to receive a transaction request. The comparison circuitry of each memory device is coupled to the programmable register and the interface circuitry to determine whether the identification information in the transaction request corresponds to the memory identification value wherein when the identification information corresponds to a memory identification value, that memory device responds to the transaction request. 
Rambus Inc.
G G G G G G G G G G G Y G G G G G G G G G G G G G G G G G G G G G G G G G
G11C G11C G06F G06F G11C G11C G11C G11C G06F G06F G11C Y02D G06F G06F G06F G11C G11C G11C G11C G06F G11C G06F G11C G06F G06F G11C G11C G06F G11C G11C G11C G11C G11C G11C G11C G11C G11C
inventional inventional inventional inventional inventional inventional additional inventional inventional inventional inventional additional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional additional inventional inventional inventional inventional inventional inventional inventional additional inventional inventional inventional inventional inventional
Mark Michael
Horowitz Farmwald