Brinks Hofer Gilson & Lione
Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect
 A semiconductor device having a high reliability passivation includes a planarization layer overlying a multi-level interconnect layer. The passivation layer has a planar surface upon which additional passivation layers are formed. Openings in the overlying passivation layers and the planarization layer expose bonding pads in the multi-level interconnect layer. In a process for fabricating the device, the planarization layer is preferably formed by dispensing a siloxane spin-on-glass (SOG) material onto the surface of the multi-level interconnect layer. The SOG is subsequently planarized to form a substantially planar surface. 
Vantis Corporation
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Xiao-Yu Sunil D.
Li Mehta