Armstrong, Westerman, Hattori, McLeland & Naughton
Memory device and a method for writing information in the memory device
 A memory device comprises a row address signal line Ax, a pair of column address signal lines Ay1, Ay2, a standby signal line Sb, a memory cell provided at an area where the row address signal line Ax intersects with the column address signal lines Ay1, Ay2, and a row address signal line driver BD provided on one end of the row address signal line. The row address signal line driver BD comprises a driver transistor BDTr of a double-emitter type, driver transistor BDTr including one collector electrode CBD, and two emitter electrodes of different areas and exhibiting negative differential characteristics. The smaller-area emitter electrode EBD1 is grounded, and the collector electrode CBD is connected to the row address signal line Ax. The driver transistor BDTr constituting the row address signal line driver BD comprises a transistor of the same structure as a transistor Tr of the memory cell, whereby a voltage of the holding state can be set at 0, and a voltage set for writing when the memory device is at a stable operating point S1 or S2 can have equal positive and negative values. Accordingly, the memory device can have a smaller number of devices and take a smaller area, and the memory cells and peripheral circuits can be easily designed. 
Fujitsu Limited
G H
G11C H01L
inventional inventional
Toshihiko
Mori