Slater & Matsil, L.L.P.
SRAM read and write assist apparatus
A SRAM READ and WRITE assist apparatus comprises a bit line voltage tracking block, a READ assist timer, a READ assist unit, a WRITE assist unit a WRITE control unit. The bit line voltage tracking block detects a voltage on a tracking bit line coupled to a plurality of tracking memory cells. In response to the voltage drop on the tracking bit line, the READ assist timer generates a READ assist pulse. When the READ assist pulse has a logic high state, an activated word line is pulled down to a lower voltage. Such a lower voltage helps to improve the robustness of SRAM memory circuits so as to avoid READ and WRITE failures.
Taiwan Semiconductor Manufacturing Company, Ltd.
G
G11C
inventional
Jonathan Tsung-Yung Chiting Chung-Cheng
Chang Cheng Chou