Antonelli, Terry, Stout & Kraus, LLP
Semiconductor memory device having an improved sense amplifier arrangement
 A semiconductor memory device in which a plurality of data lines of a memory array comprising storage transistors arranged in a matrix form as those having a high or low threshold voltage according to stored data are divided into a plurality of blocks, and sense amplifiers for performing amplification operations dispersedly in time are used to amplify signals. Moreover, a first and a second group of sense amplifiers corresponding to odd- and even-numbered adjoining data lines are arranged so that while the output signals of one group of sense amplifiers are output, word lines are switched, and the other group of sense amplifiers are caused to perform the operation of amplifying the signals read from the memory cells corresponding to the word lines thus switched, respectively. 
Hitachi, Ltd.
G G G
G11C G11C G11C
inventional inventional inventional
Keiichi Hiroshi Tetsuya
Yoshida Sato Tsujikawa