IP & T Group LLP
Anti-fuse, anti-fuse array and method of operating the same
An anti-fuse, an anti-fuse array and a method of operating the same are disclosed. The anti-fuse array includes: an active region formed in a semiconductor substrate; a slit region formed at both edge portions of the active region in a first direction; a plurality of select gates extending in a second direction perpendicular to the first direction of the active region, and coupled to a select word line; a plurality of first program gates spaced apart from the select gates, formed over the active region isolated by the slit region, and coupled to a first program word line; a plurality of second program gates spaced apart from the select gates, formed over the active region isolated by the slit region, and coupled to a second program word line; and a bit line perpendicular to the select word line.
SK Hynix Inc.
G G H H H
G11C G11C H01L H01L H01L
inventional inventional inventional additional additional
Yong Sun
Jung