Jianq Chyun IP Office
Logic gate
A logic gate including a first resistive non-volatile memory device and a second resistive non-volatile memory device is provided. When top electrodes of the first and the second resistive non-volatile memory devices are coupled to an output terminal of the logic gate, bottom electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to a first input terminal and a second input terminal of the logic gate. When the bottom electrodes of the first and the second resistive non-volatile memory devices are coupled to the output terminal of the logic gate, the top electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to the first input terminal and the second input terminal of the logic gate.
Industrial Technology Research Institute
H H H H
H03K H01L H01L H03K
inventional additional additional inventional
Zhe-Hui Wen-Pin Chih-He Yu-Sheng
Lin Lin Lin Chen