Merchant & Gould P.C.
Mixed threshold voltage memory array
A static random access memory (SRAM) device includes a first memory array including a plurality of memory cells, each memory cell including a first pass gate transistor with a first threshold voltage connected to a bit line. The SRAM device further includes a second memory array including a plurality of memory cells, each memory cell including a second pass gate transistor with a second threshold voltage connected to the bit line. The SRAM device further includes a peripheral input-output circuit connected to the bit line. The SRAM device still further includes a column of write current tracking cells, each tracking cell disposed within a row of the first memory array and the second memory array, wherein the first memory array is between the peripheral input-output circuit and the second memory array.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H G G G G G G
H01L G11C G11C G11C G11C G11C G11C
additional inventional inventional inventional inventional inventional inventional
Chih-Yu Wei-Chang Hidehiro
Lin Zhao Fujiwara