Eschweiler & Potashnik, LLC
Field plate structure for high voltage device
Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a source region and a drain region within a substrate. A drift region is formed within the substrate such that the drift region is disposed laterally between the source region and the drain region. A first gate structure is formed over the drift region. An inter-level dielectric (ILD) layer is formed over the first gate structure. The ILD layers is patterned to define a field plate opening. A first field plate layer, a second field plate layer, and a third field plate layer are formed within the field plate opening.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Jyun-Guan Pei-Lun Yu-Chang Hui-Ting Chia-Cheng
Jhou Wang Jong Lu Ho