McGinn & Gibb, P.C.
Single-chip synchronous dynamic random access memory (DRAM) system including first address generator operable in first and second modes
 To obtain high access speed regardless of a structure and operating characteristics of an external central processing unit (CPU), a synchronous dynamic random access memory (DRAM) system includes first and second DRAM cell arrays, and a first address generator for outputting a first address and a second address respectively to the first and second DRAM cell arrays simultaneously in a first mode. In a second mode, the first address generator outputs the first address and the second address respectively to the first and second DRAM cell arrays sequentially. 
NEC Corporation
G G
G11C G11C
inventional inventional
Mamoru
Fujita