Haynes and Boone, LLP
Layout optimization for integrated circuit design
A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.
Taiwan Semiconductor Manufacturing Company, Ltd.
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inventional inventional additional additional inventional
Lee-Chung Huang-Yu Yu-Hsiang Yuan-Te Ken-Hsien Ru-Gun
Lu Chen Kao Hou Hsieh Liu