Conley, Rose & Tayon, P.C.
Microprocessor having address generation units for efficient generation of memory operation addresses
 A microprocessor including address generation units configured to perform address generation for memory operations is provided. A reservation station associated with one of the address generation units receives the displacement from an instruction and an indication of the selected segment register upon decode of the instruction in a corresponding decode unit within the microprocessor. The displacement and segment base address from the selected segment register are added in the reservation station while the register operands for the instruction are requested. If the register operands are provided upon request (as opposed to a reorder buffer tag), the displacement/base sum and register operands are passed to the address generation unit. The address generation unit adds the displacement/base sum to the register operands, thereby forming the linear address. If register operands are not provided upon request (i.e. one or more reorder buffer tags are received instead of the corresponding register operand), then the reservation station stores the displacement/base sum and register operands/tags. Once each register operand has been provided, the displacement/base sum and register operands are conveyed to the address generation unit. Data address generation responsibilities are thereby fulfilled by the address generation units. Since the functional units of the microprocessor are relieved of address generation responsibilities, the functional units may be simplified. 
Advanced Micro Devices, Inc.
G G
G06F G06F
inventional inventional
Rupaka Thang M.
Mahalingaiah Tran