Wilson, Sonsini, Goodrich & Rosati
Flash memory device with multiple checkpoint erase suspend logic
 A flash memory device includes a multiple checkpoint erase suspend algorithm. A user may issue an erase suspend command at anytime during an erase process. The erase procedure is suspended as fast as possible by allowing the erase procedure to be suspended at the first to occur of a plurality of checkpoints in the process. The block erase procedure includes a precondition phase (also called a pre-programming phase), in which a selected block is pre-programmed by applying a program potential, and then the pre-programming of the block is verified on a byte-by-byte basis. After the precondition phase, an erase phase is executed in which the selected block is erased by applying an erase potential to the block, and then verifying the erasing of the block. Erase suspend logic is coupled to the erase logic and executes an erase suspend procedure which interrupts the block erase procedure after receiving the erase suspend command during the first to occur of a set of checkpoints in the block erase procedure. The set of checkpoints comprises a first checkpoint enabling the interrupting during the precondition phase, a second checkpoint enabling the interrupting during the application of the erase potential, a third checkpoint enabling the interrupting during the verifying of the erasing step, a fourth checkpoint between the precondition phase and the erase phase, and a fifth checkpoint after the erase pulse and before verifying the erase of the block. After interrupting the block erase procedure, the erase suspend procedure includes returning to the block erase procedure to complete the block erase. 
Macronix International Co., Ltd.
G G
G11C G11C
additional inventional
Weitong Tzeng-Huei Yu-Sui Kong Mou Ray-Lin
Chuang Shiau Lee Liou Wan