Birch, Stewart, Kolasch & Birch, LLP
Electrostatic discharge protection circuit
An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.
Vanguard International Semiconductor Corporation
H H
H01L H02H
inventional inventional
Yu-Kai Shao-Chang Li-Fan Ting-You Hung-Wei Chun-Chih Chih-Hsuan Ching-Wen
Wang Huang Chen Lin Chen Chen Lin Wang