Volentine & Whitt, PLLC
Variable resistance memory device and system
A semiconductor memory device includes a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.
Samsung Electronics Co., Ltd.
G G
G11C G11C
inventional inventional
Taek-Sung Hyun-Ho Kwang-Jin Qi Woo-Yeong Kwang-Ho
Kim Choi Lee Wang Cho Kim