Slater & Matsil, L.L.P.
Method for forming self-assembled mono-layer liner for cu/porous low-k interconnections
A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Tien-I Keng-Chu Chen-Hua Chung-Chi Chia-Cheng
Bao Lin Yu Ko Chou