Christie, Parker & Hale
Temporary bus master for use in a digital system having asynchronously communicating sub-systems
 A circuit embodied in a single integrated circuit, which is connected through an asynchronous communication bus to a primary bus master and a permanent bus slave, cooperates with the master and slave in a multi-master transfer of a block of data having a leading sub-block of data followed by a trailing sub-block of data. The slave operates in accord with request/acknowledge protocol by applying at least one request signal to a conductor of the bus and responding to each of a consecutive sequence of acknowledge signals on a second conductor of the bus from the master in communication of each of a consecutive sequence of concurrently-applied parallel-by-bit data carried by multiple other conductors that define a data bus portion of the communication bus. The circuit selectively responds to each of a predetermined number of acknowledge signals from the master during communication of the leading sub-block, by copying each data item of the leading sub-block, so that the leading sub-block is distributed to the circuit as it is communicated between the master and the slave. The circuit selectively responds to request signals by applying a second predetermined number of acknowledge signals to the second conductor while participating in communication of each data item of the trailing sub-block. A bi-directional buffer receives the acknowledge signals during the transfer of the leading sub-block and applies the acknowledge signals during the transfer of the trailing sub-block. 
Western Digital Corporation
G G
G06F G06F
inventional inventional
Takashi Rajni N.
Asami Doshi