Power/ground layout for chips
Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.
Marvell World Trade Ltd.
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Weidan Sehat Chung Chyung Chuan-Cheng Shuhua Albert
Li Sutardja Han Cheng Yu Wu