JCIPRNET
Memory device and multi-level memory cell having ferroelectric storage element and magneto-resistive storage element
A memory device includes a plurality of word lines, a plurality of bit lines, a plurality of source lines and a plurality of multi-level memory cells is introduced. Each of the multi-level memory cells is coupled to one of the word lines, one of the bit lines and one of the source lines. Each of the multi-level memory cells includes a ferroelectric storage element and a magneto-resistive storage element cascaded to the ferroelectric storage element. The ferroelectric storage element is configured to store a first bit of a multi-bit data. The magneto-resistive storage element is configured to store a second bit of the multi-bit data.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Tzu-Chiang Chih-Sheng Chao-Ching Jin Hung-Li
Chen Chang Cheng Cai Chiang