Heller Ehrman LLP
Semiconductor memory device for performing refresh operation
A semiconductor memory device including a sensing control unit, a separation control unit and a sense amplifier enable unit. The sensing control unit outputs a plurality of mat enable signals in response to a mat selecting signal, a clock enable signal, a refresh signal and a test mode signal. The separation control unit outputs a plurality of separation control signals which control driving of a separation transistor adjacent to the mat in response to the plurality of mat enable signals. The sense amplifier enable unit outputs a sense amplifier enable signal for controlling driving of the sense amplifier in response to the clock enable signal, the mat selecting signal, the test mode signal and the refresh signal. In the semiconductor memory device, a refresh operation is performed at an unlimited sense amplifier test mode.
Hynix Semiconductor Inc.
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Seong Jun
Lee