Fernandez & Associates LLP
Structure and method of a column redundancy memory
 A memory architecture is disclosed that employs multiple column redundancies which provide multiple options for replacing a defective global odd or even bit line. Each column memory has two multiplexers, one for selecting a global odd bit line and another for selecting a global even bit line. Two or more column redundancies are coupled to each of the multiplexer in the column memory. In a first embodiment, the global odd and even bit lines are connected through odd and even sense amps in a regular column. In a second embodiment, the global odd bit line in a regular column connects through odd sense amps, while the global even bit line in the regular column connects through even sense amps. In a third embodiment, two or more sets of redundancy columns are commonly coupled to a left adjacent regular column and a right adjacent regular column. 
Silicon Access Networks, Inc.
G
G11C
inventional
Hing Juhan
Wong Kim