EEPROM cell with self-aligned tunneling window
An improved EEPROM cell with a self-aligned tunneling window is provided which is fabricated by a standard STI process so as to produce a smaller layout size and a reduced cell height. The EEPROM cell includes a floating gate, a programmable junction region, and a tunneling oxide layer separating the programmable junction region and the floating gate. The length dimension of the floating gate is less than the length dimension of the tunneling window so that the tunneling window is overlapping the floating gate. The tunneling window is self-aligned by edges forming the length dimension of the floating gate so as to form a self-aligned tunneling window.
Lattice Semiconductor Corporation
H
H01L
inventional
Christopher O. Sunil D. Xiao Yu
Schmidt Mehta Li