Harness, Dickey & Pierce, P.L.C.
Semiconductor memory device and redundancy method of the same
A semiconductor memory device may include a memory cell array, a redundancy address decoder, a defective address detection unit, and a defective address program unit. The memory cell array includes a plurality of memory cell groups and a predetermined number of redundancy memory cell groups. The redundancy address decoder includes a predetermined number of redundancy decoders for accessing at least one group of the redundancy memory cell groups when a first defective address is identical to an externally applied address. The defective address detection unit performs a write operation and a read operation on the memory cell array during a test operation to detect a defective address, and outputs the detected defective address as the first defective address when the same defective address is detected a predetermined number of times or more. The defective address program unit receives and programs the first defective address output from the defective address detection unit during a program operation.
Samsung Electronics Co., Ltd.
G G G G G G
G11C G11C G06F G11C G11C G11C
additional inventional inventional inventional additional inventional
Yun-Sang
Lee