Liu & Liu
Wafer level array of chips and method thereof
A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.
XINTEC INC.
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inventional additional additional additional additional additional additional additional additional additional additional inventional additional additional additional additional additional additional additional additional additional additional additional additional additional additional inventional inventional inventional additional inventional additional inventional additional
Chia-Ming Tsang-Yu Chun-Wei Chia-Sheng Chien-Hui Kuei-Wei
Cheng Liu Chang Lin Chen Chen