Dual comparator-based error correction scheme for analog-to-digital converters
An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is configured to output a first output voltage and the second comparator is configured to output a second output voltage during a same binary algorithmic iteration of the ADC. The decision timing comparison logic unit is configured to identify a first polarity of the first output voltage and a second polarity of the second output voltage and, if the first polarity is equivalent to a second polarity, to insert at least one redundant capacitor for a next binary algorithmic iteration of the ADC.
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Arup Seung Bae Sriram Ajit Srinath M.
Polley Lee Narayanan Sharma Ramaswamy