Haynes and Boone, LLP
Method and apparatus for reducing implant topography reflection effect
Embodiments of the present disclosure provide methods and apparatuses for integrated circuits. An exemplary integrated circuit (IC) method includes providing an IC design layout that includes a design feature; determining a dimensional difference between the design feature and a corresponding developed photoresist feature of a photoresist layer; modifying the CD of the design feature to compensate for the difference, thereby generating a modified IC design layout; and making a mask using the modified IC design layout.
Taiwan Semiconductor Manufacturing Company, Ltd.
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G03F G03F
inventional inventional
Hsien-Huang Chi-Cheng Wen-Chun Ru-Gun Wen Hao
Liao Hung Huang Liu Liu