Finnegan, Henderson, Farabow, Garrett &
Converter producing three output states
 An output circuit is provided in which a first IG-FET of a first conductivity type is connected between a first potential supply terminal and an output terminal and having its substrate controlled by a third potential higher than the first potential of the first potential supply terminal and a second IG-FET of a second conductivity type connected between a second potential supply terminal having a second potential lower than the first potential and the output terminal and having its substrate electrode supplied with the second potential. A control circuit is further provided which receives an input signal and control signal and controls the output circuit to permit the latter to produce one of the first potential, second potential and high impedance state. The output circuit and control circuit are combined to provide a converter circuit for converting the level of a CML (complementary MOS Transistor Logic) to a TTL (Transistor-Transistor Logic). A compensation circuit is further provided which, when a potential on the output terminal is shifted from the second potential to the first potential, permits a rise of the second potential to be sharpened. The compensation circuit includes a third IG-FET of a second conductivity type connected between the first potential supply terminal and the output terminal. 
Tokyo Shibaura Denki Kabushiki Kaisha
H H
H03K H03K
inventional inventional
Ryuzo Yasoji
Shiraki Suzuki