Method of manufacturing complementary metal oxide semiconductor transistors
A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.
United Microelectronics Corp.
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Chia-Wen Shyh-Fann Chih-Chiang Cheng-Tung Meng-Yi Wen-Han Li-Shian Tzyy-Ming Shih-Chieh Kun-Hsien
Liang Ting Wu Huang Wu Hung Jeng Cheng Hsu Lee