Multi-port high performance memory
A structure includes a multi-port memory including a multiple transistor bitcell single ended read port and a write port, a read circuit which is connected to a multiple transistor bitcell circuit and is also configured to evaluate the multiple transistor bitcell single ended read port, and a timer circuit for the single ended read port and which is configured to generate two successive read pulses in one clock cycle for the multi-port memory.
Marvell Asia Pte, Ltd.
G G G G G
G11C G11C G11C G11C G11C
additional inventional inventional inventional inventional
Yuzheng Qing Shuangdi Hao Wei Igor George M. Xiaoli
Jin Li Zhao Pu Zhao Arsovski Braceras Hu