Haynes and Boone, LLP
Method and structure improving isolation between memory cell passing gate and capacitor
A memory cell comprising a capacitor having a dielectric layer interposing first and second vertically disposed electrodes, an insulating lining located over the capacitor, and a transistor gate extension passing over the capacitor. A spacer isolates an end of one of the capacitor electrodes from the transistor gate extension. In one embodiment, the spacer includes a first non-planar profile configured to engage a second non-planar profile comprising ends of the one of the capacitor electrodes and the insulating lining.
Taiwan Semiconductor Manufacturing Company, Ltd.
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inventional additional inventional
Chun-Yao Tien-Lu Kuo-Ching Chung-Wei Wen-Cheng Kuo-Chi Hsiao-Hui Huey-Chi Tsung-Hsun
Chen Lin Huang Chang Chen Tu Tseng Chu Huang