Finnegan, Henderson, Farabow & Garrett
Semiconductor memory with data detection circuit
 Provided is a semiconductor memory device comprising a pair of data input lines, a pair of data output lines, memory cells arranged in the form of a matrix, the memory cell of each column being connected between a pair of data lines, the memory cell of each row being connected to a row selection line, a memory cell selection circuit for generating column and row designation signals in order to select a desired one of said memory cells, a switching circuit disposed in each column and turned on upon receipt of a column designation signal from the memory cell selection circuit to connect the data line to a corresponding one of the data input lines, and a data detection circuit connected between the pair of data lines of each column and adapted, upon receipt of a column signal from the memory cell selection circuit, to transmit an inverted signal of a signal on the data line onto the data output line. 
Tokyo Shibaura Electric Co., Ltd.
G G
G11C G11C
inventional inventional
Yasoji Kiyofumi
Suzuki Ochii