Maschoff Brennan
Cell layout of semiconductor device
A device is disclosed that includes a cell block, at least one first metal interconnect, and second metal interconnects. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The at least one first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the at least one first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the at least one first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed.
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
G G G G
G06F G06F G06F G06F
inventional inventional inventional additional
Yi-Lin Huang-Yu Yun-Han
Chuang Chen Lee