Tutunjian & Bitetto, P.C.
Integrated strained stacked nanosheet FET
Transistors include multiple stress liners. One or more channel structures are suspended at opposite ends from the plurality of stress liners. The stress liners provide a stress on the one or more channel structures. A gate is formed over and around the one or more channel structures, defining a channel region of the one or more channel structures that is covered by the gate. A source and drain region are formed on opposite sides of the gate.
International Business Machines Corporation
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Juntao Ramachandra Kangguo Xin
Li Divakaruni Cheng Miao