Conley, Rose & Tayon
Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache
 An apparatus including a banked instruction cache and a branch prediction unit is provided. The banked instruction cache allows multiple instruction fetch addresses (comprising consecutive instruction blocks from the predicted instruction stream being executed by the microprocessor) to be fetched concurrently. The instruction cache provides an instruction block corresponding to one of the multiple fetch addresses to the instruction processing pipeline of the microprocessor during each consecutive clock cycle, while additional instruction fetch addresses from the predicted instruction stream are fetched. Preferably, the instruction cache includes at least a number of banks equal to the number of clock cycles consumed by an instruction cache access. In this manner, instructions may be provided during each consecutive clock cycle even though instruction cache access time is greater than the clock cycle time of the microprocessor. Because consecutive instruction blocks from the instruction stream are fetched concurrently, the branch prediction unit stores a prediction for a non-consecutive instruction block with each instruction block. For example, for an instruction cache having a cache access time which is twice the clock cycle time, a prediction for the second consecutive instruction block following a particular instruction block within the predicted instruction stream is stored. When a pair of consecutive instruction blocks are fetched, predictions for a second pair of consecutive instruction blocks within the instruction stream subsequent to the pair of consecutive instruction blocks are formed from the branch prediction information stored with respect to the pair of consecutive instruction blocks. 
Advanced Micro Devices, Inc.
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Thang M.
Tran