Qualcomm Incorporated Toler
Electrode structure for resistive memory device
A method includes patterning a photo resist layer on top of a semiconductor device. The semiconductor device includes a lower portion, a capping layer formed on top of the lower portion, and an optional oxide layer formed on top of the capping layer. The lower portion includes a dielectric material and an interconnect. The method also includes etching portions of the semiconductor device based on the photo resist layer to expose the interconnect. The method further includes depositing a bottom electrode of a resistive memory device on the interconnect. The bottom electrode is comprised of cobalt tungsten phosphorus (CoWP).
QUALCOMM Incorporated
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Xia Junjing Yu Seung Hyuk
Li Bao Lu Kang