Harness, Dickey & Pierce, PLC
Capacitorless memory device
According to an example embodiment of inventive concepts, a capacitorless memory device includes a capacitorless memory cell that includes a bit line on a substrate; a read transistor, and a write transistor. The read transistor may include first to third impurity layers stacked in a vertical direction on the bit line. The first and third layers may be a first conductive type, and the second impurity layer may be a second conductive type that differs from the first conductive type. The write transistor may include a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate, and a gate line that is adjacent to a side surface of the body layer. The gate line may be spaced apart from the side surface of the body layer. The source layer may be adjacent to a side surface of the second impurity layer.
Samsung Electronics Co., Ltd.
H H H
H01L H01L H01L
inventional inventional inventional
Seung-Uk Jin-Seong Nam-Ho Jun-Su Satoru Jae-Hoon
Han Lee Jeon Kim Yamada Lee