Low offset voltage AlInAs/GaInAs heterostructure-confinement bipolar transistor
 The present provides two low offset voltage AlInAs/GaInAs heterostructure-confinement bipolar transistors which include AlInAs heterostructure-confinement and AlInAs/GaInAs superlattice-confinement bipolar transistors. In the present invention, an n GaInAs emitter layer is inserted at AlGaAs confinement layer/GaInAs base layer to reduce offset voltage and potential spike at an E-B junction. 
National Science Council
H
H01L
inventional
Wen-Shiung Wen-Chau Jung-Hui
Lour Liu Tsai