Harness, Dickey & Pierce, PLC
Test method of semiconductor memory device and semiconductor memory system transferring fail address data from a volatile to a non-volatile memory array using an error-correction code engine
A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area.
SAMSUNG ELECTRONICS CO., LTD.
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Hak-Soo Sua Sung Hyun Hyojin Dongsoo Jun Hee Jinsu Jaeyoun Chulwoo
Yu Kim Lee Choi Kang Yoo Jung Youn Park