Morrison & Foerster LLP
Method of manufacturing semiconductor device with two-step etching of layer
The invention is directed to improvement of reliability of a process of separating a layer to be patterned such as a wiring layer in a semiconductor device manufacturing method. A wiring layer is formed on a back surface of a semiconductor substrate. A third resist layer (positive resist layer) is formed on the wiring layer, having an opening in a predetermined region along a dicing line at a bottom of the opening, and the wiring layer is etched using the third resist layer as a mask. After the third resist layer is removed, a fourth resist layer (negative resist layer) is formed on the wiring layer so as to leave the wiring layer in a region of a predetermined pattern, and the wiring layer is etched using the fourth resist layer as a mask. The wiring layer is thus patterned so as to form the predetermined pattern and be separated at the predetermined region along the dicing line at the bottom of the opening without fail.
Sanyo Electric Co., Ltd.
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Keiichi Hiroshi
Yamaguchi Yamada