Cooper Legal Group, LLC
Phase-locked loop (PLL)
A phase-locked loop (PLL) is provided. The PLL comprises a dithering circuit that is configured to receive a second tuning signal, and dither the second tuning signal to generate a dither signal to decrease a magnitude of a spur of the PLL. The dither signal is used by a digitally controlled oscillator (DCO) to generate an output signal of the PLL. Operation of the dithering circuit is controlled using a spur-cancel control circuit. The spur-cancel control circuit receives a frequency command word (FCW) signal and determines a value of an enable signal based on the FCW signal. In some embodiments, the dithering circuit dithers the second tuning signal based on the enable signal.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
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additional inventional inventional
Lee Tsung Kuang-Kai Robert Bogdan Huan-Neng Feng Wei Chewn-Pu
Hsiung Yen Staszewski Chen Kuo Jou