Sughrue, Mion, Zinn, Macpeak & Seas
Semiconductor memory device having dual word line structure
 A dynamic random access memory device of a dual word line structure is disclosed, which comprises a plurality of memory array blocks, each of the memory array blocks including at least one main-word line, a plurality of sub-word lines, a plurality of sub-word drivers having an input node connected to the main-word line, an output node connected to an associated one of the sub-word lines and a power node, each of the sub-word drivers responding to an active level of the main-word line to drive the associated sub-word line with a power voltage supplied to the power node, and a decoding unit for, when activated, supplying the power voltage to the power nodes of the sub-word line drivers, and the decoding unit of one of the memory array blocks being activated in response to address information. 
NEC Corporation
G G
G11C G11C
inventional inventional
Mamoru
Fujita