Blakely, Sokoloff, Taylor & Zafman
Integrated circuit I/O using a high performance bus interface
 A dynamic random access memory (DRAM). The DRAM comprises a first circuit for providing a clock signal and a conductor for coupling the DRAM to a bus. A receiver circuit is coupled to the conductor and the first circuit for latching information received from the conductor in response to detecting each of a rising edge of the clock signal and a falling edge of the clock signal. The receiver circuit may include a first input receiver for latching information in response to the rising edge of the clock signal and a second input receiver for latching information in response to the falling edge of the clock signal. 
Rambus, Inc.
G G G G G G G G G G Y G G G G G G G G G G G G G G G G G G G G G G G G G G
G11C G06F G11C G11C G11C G11C G11C G11C G06F G11C Y02D G11C G11C G06F G11C G06F G11C G11C G06F G11C G11C G11C G06F G11C G11C G06F G11C G11C G11C G06F G06F G06F G11C G06F G11C G11C G06F
inventional inventional inventional inventional inventional inventional inventional inventional additional inventional additional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional additional inventional inventional additional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional
Mark Michael
Horowitz Farmwald