Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of GATE-snake-open-configured, NCEM-enabled fill cells
Improved processes for manufacturing wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured to target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes, including GATE-snake-open and/or GATE-snake-resistance failure modes. Such processes may involve evaluating Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).
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Conor Kelvin Timothy Carl Marcin Nobuharu Dennis Hans Vyacheslav Tomasz Rakesh Marci Kimon John Jeremy Jonathan Stephen Hideki Andrzej Markus Sherry Larg Christopher Simone Indranil Sheng-Che
O'Sullivan Doong Fiscus Taylor Strojwas Yokoyama Ciplickas Eisenmann Rovner Brozek Vallishayee Liao Michaels Kibarian Cheng Haigh Lam Matsuhashi Strojwas Rauscher Lee Weiland Hess Comensoli De Lin