Antonelli, Terry, Stout & Kraus
Parallel processor having multi-processing units either connected or bypassed in either series or parallel by the use of bus switching
 A parallel process which includes a plurality of processing units connected to each other via input/output ports. Each of the plurality of processing units includes a memory for storing a program and data, a local bus for inputting/outputting the program and data to and from the memory having an address signal line, a data signal line, and a control signal line, a CPU for reading the program from the memory via the local bus, reading data needed to execute the program from the memory via the local bus, and storing data which has been updated due to the execution of the program in the memory via the local bus, and a plurality of input/output ports for connecting the local bus to a plurality of outside buses. The input/output ports are used by the CPU to input/output data to and from an outside memory connected to an outside bus or by an outside CPU, connected to an outside bus, to input/output data to and from the memory. At least one bypass switch is provided for controllably connecting two of the outside buses to permit data transference between the outside CPU and the outside memory thereby bypassing the CPU and the memory. Also provided is a main CPU for setting program and data in the processing units and recovering data from the processing units. 
Hitachi, Ltd.
G G
G06F G06F
inventional inventional
Koyo Hiromichi
Katsura Yamada