Eschweiler & Associates, LLC
Area optimized series gate layout structure for FINFET array
The present disclosure relates to a method of optimizing the area of series gate layout structures for FinFET devices. The method analyzes an integrated chip (IC) layout to determine a first gate material density along a first direction and to separately determine a second gate material density along a second direction based upon the first gate material density. A number of series gate stages for a FinFET (field effect transistor) device having a gate length along the second direction, is chosen based upon the second gate material density and one or more device performance parameters of the FinFET device. By analyzing the density of gate material in separate directions, the effective length of the gate of the FinFET can be increased without increasing the size of the transistor array.
Taiwan Semiconductor Manufacturing Co., Ltd.
G
G06F
inventional
Chin-Hua Wen-Shen Chih-Chiang Yung-Chow
Wen Chou Chang Peng