Hauptman Ham, LLP
Mask shift resistance-inductance method for multiple patterning mask design and a method for performing the same
A system and method comprising providing a layout of an integrated circuit design, generating, by a processor, a plurality of multiple patterning decompositions from the layout, determining a maximum mask shift between the first mask and the second mask and simulating a worst-case performance value for each of the plurality of multiple patterning decompositions using one or more mask shifts within a range defined by the maximum mask shift. Further, each of the plurality of multiple patterning decompositions comprise patterns separated to a first mask and a second mask of a multiple patterning mask set.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
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inventional inventional inventional inventional
Te-Yu Chih-Cheng Ke-Ying Hsien-Hsin Sean
Liu Chou Su Lee