Haynes and Boone, LLP
Layout optimization for integrated circuit design
A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
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Yu-Hsiang Ru-Gun Ken-Hsien Huang-Yu Yuan-Te Lee-Chung
Kao Liu Hsieh Chen Hou Lu