Volpe and Koenig, P.C.
Extreme-bandwidth scalable performance-per-watt GPU architecture
A technique for accessing memory in an accelerated processing device coupled to stacked memory dies is provided herein. The technique includes receiving a memory access request from an execution unit and identifying whether the memory access request corresponds to memory cells of the stacked dies that are considered local to the execution unit or non-local. For local accesses, the access is made “directly”, that is, without using a bus. A control die coordinates operations for such local accesses, activating particular through-silicon-vias associated with the memory cells that include the data for the access. Non-local accesses are made via a distributed cache fabric and an interconnect bus in the control die. Various other features and details are provided below.
ADVANCED MICRO DEVICES, INC.
G G G G G G G G Y G G G G G
G06F G06F G06F G06F G06F G06F G06T G06F Y02D G06T G06F G06F G06F G06F
inventional inventional additional inventional inventional inventional inventional additional additional additional inventional inventional inventional inventional
Jiasheng Dmitri
Chen Yudanov