Fish & Richardson P.C.
Semiconductor memory device and semiconductor device
A matrix is formed using a plurality of memory cells in each of which a drain of the writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor. A gate of the writing transistor, a source of the writing transistor, a source of the reading transistor, and a drain of the reading transistor are connected to a writing word line, a writing bit line, a reading bit line, and a bias line, respectively. In order to reduce the number of wirings, a writing word line to which the gate of the writing transistor is not connected is substituted for the reading word line. Further, the writing bit line is substituted for the reading bit line.
Semiconductor Energy Laboratory Co., Ltd.
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Yasuhiko Kiyoshi Shunpei Jun
Takemura Kato Yamazaki Koyama