Haynes and Boone, LLP
Method for integrated circuit manufacturing
Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.
Taiwan Semiconductor Manufacturing Company, Ltd.
G G G G G H
G03F G06F G06F G06F G03F H01L
inventional additional inventional additional inventional additional
Ru-Gun Wen-Chun Ching-Hsu Wen-Hao Feng-Lung Cheng Kun Hung-Chun Chun-Hung Feng-Ju Ming-Hsuan Ping-Chieh
Liu Huang Chang Liu Lin Tsai Wang Wu Chang Wu Wu