Sheridan Ross P.C.
Memory unit
In a memory unit according to an embodiment of the present disclosure, a memory cell array is configured, when, of a plurality of memory cells, multiple first memory cells whose corresponding fourth wiring line and first wiring line are different from one another are simultaneously accessed, to allow for simultaneous access to the multiple first memory cells, without allowing for simultaneous access to memory cells corresponding to the fourth wiring line shared by the first memory cells.
Sony Semiconductor Solutions Corporation
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H01L H01L G11C G11C H01L G11C H01L H01L
inventional inventional additional additional inventional inventional inventional inventional
Makoto Yotaro Haruhiko Yoshiyuki
Kitagawa Mori Terada Shibahara