Oblon, Fisher, Spivak, McClelland & Maier
High-speed refreshing rechnique for highly-integrated random-access memory
 A divided-bit line type dynamic random-access memory is disclosed which has parallel main bit line pairs in each of which sub-bit line pairs are provided to be electrically parallel with each other. Parallel word lines are provided on the substrate to insulatively cross the sub-bit line pairs. Memory cells are connected to crossing points of the sub-bit line pairs and the word lines. Main sense amplifiers are respectively connected to the main bit line pairs, sub-sense amplifiers are respectively connected to the sub-bit line pairs. A specific refreshing technique is utilized, according to which, when a refreshing operation is executed in a refreshing mode of the memory, the same number of word lines as that of sub-bit line pairs provided in each main-bit line pair are simultaneously selected, and the sub-sense amplifiers are activated to refresh together the memory cells which are connected to the work lines thus selected. 
Kabushiki Kaisha Toshiba
G G
G11C G11C
inventional inventional
Koji Shigeyoshi
Sakui Watanabe