Memory device having write latency
 A memory device having a plurality of memory cells, the memory device comprising clock receiver circuitry to receive an external clock signal, and input receiver circuitry to sample, in response to a write request, a first portion of data after a number of clock cycles of the external clock signal transpire. The first portion of data is sampled synchronously with respect to the external clock signal. 
Rambus Inc.
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Michael Mark
Farmwald Horowitz