Buffer circuit having Schottky gate transistors adjusting amplitude of output signal
A buffer circuit having an input and output terminals includes a first Schottky gate transistor connected between a voltage setting node and ground, a load device connected between a power supply and the voltage setting node, a second Schottky gate transistor connected between the output terminal and ground, the gate of the second Schottky gate transistor being connected to the voltage setting node, a third Schottky gate transistor connected between the output terminal and the power supply, the gate of the third Schottky gate transistor being connected to the input terminal, a resistor means connected the gate of the first Schottky gate transistor and input terminal for increasing a voltage level applied to the gate of the third Schottky gate transistor.
Oki Electric Industry Co., Ltd.
H
H03K
inventional
Hiroyuki
Yamada