Conley, Rose & Tayon, PC
Load/store unit with multiple oldest outstanding instruction pointers for completing store and load/store miss instructions
 A superscalar microprocessor is provided having a load/store unit which receives a pair of pointers identifying the oldest outstanding instructions which are not in condition for retirement. The load/store unit compares these pointers with the reorder buffer tags of load instructions that miss the data cache and store instructions. A match must be found before the associated instruction accesses the data cache and the main memory system. The pointer-compare mechanism provides an ordering mechanism for load instructions that miss the data cache and store instructions. 
Advanced Micro Devices, Inc.
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Thang M.
Tran