High speed asynchronous and programmable state machine for generating almost full synchronous flags in a synchronous FIFO
A state machine comprising a first input receiving a first read clock, a second input receiving a first write clock, a third input receiving a first programmable Almost Full look-ahead signal, a fourth input receiving a second read clock, a fifth input receiving a second write clock, and a sixth input receiving a second programmable Almost Full look-ahead signal is disclosed. The state machine manipulates the inputs to produce an output signal representing an Almost Full output flag that is at a first logic state when a FIFO is Almost Full and is at a second logic state when the FIFO is Not Almost Full.
Cypress Semiconductor Corp.
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additional inventional
Parinda Johnie Chia Jen
Mekara Au Chang