Blakely, Sokoloff, Taylor & Zafman LLP
Low sheet resistance GaN channel on Si substrates using InAlN and AlGaN bi-layer capping stack
Transistors or transistor layers include an InAlN and AlGaN bi-layer capping stack on a 2DEG GaN channel, such as for GaN MOS structures on Si substrates. The GaN channel may be formed in a GaN buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between GaN and Si. The bi-layer capping stack an upper InAlN layer on a lower AlGaN layer to induce charge polarization in the channel, compensate for poor composition uniformity (e.g., of Al), and compensate for rough surface morphology of the bottom surface of the InAlN material. It may lead to a sheet resistance between 250 and 350 ohms/sqr. It may also reduce bowing of the GaN on Si wafers during growth of the layer of InAlN material, and provide a AlGaN setback layer for etching the InAlN layer in the gate region.
Intel Corporation
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Sanaz K. Robert S. Seung Hoon Han Wui Marko Sansaptak Benjamin
Gardner Chau Sung Then Radosavljevic Dasgupta Chu-Kung