Finnegan, Henderson, Farabow, Garrett & Dunner
Dynamic semiconductor memory device
 A semiconductor memory device has N sense amplifiers each having first and second input terminals, N first memory cells, N second memory cells, N first bit lines each of which is connected to the first memory cells of the same column and connected to the first input terminal of one of the sense amplifiers, and N second bit lines each of which is connected to the second memory cells of the same column and connected to the second input terminal of one of the sense amplifiers. The first memory cells are formed in a first memory cell area and the second memory cells are formed in a second memory cell area arranged adjacent to the first memory cell area and on the same side as the first memory cell area with respect to the sense amplifiers. 
Kabushiki Kaisha Toshiba
G G G
G11C G11C G11C
inventional inventional inventional
Tatsuo Tohru Shigeyoshi
Ikawa Furuyama Watanabe