Eschweiler & Associates, LLC
Over stress verify design rule check
Some aspects of this disclosure provide for electronic design automation (EDA) techniques that check whether individual blocks, such as transistors or other semiconductor devices, are connected to their correct power domains during design. In this way, the disclosed EDA techniques can limit or prevent overstress conditions applied to blocks and help to improve reliability of integrated circuits, when manufactured.
Taiwan Semiconductor Manufacturing Co., Ltd.
G G
G06F G06F
additional inventional
Chih-Hsien Chen-Ting Yung-Chow
Chang Ko Peng