Independent array grounds for flash EEPROM array with paged erase architechture
 An improved architecture for an array of flash EEPROM cells with paged erase is provided. The array is formed of a plurality of half-sectors. In each sector, the sources of the memory cell transistors are connected to a separate individual ground line. A ground line circuit is provided for generating a half-sector ground line signal. The separate individual ground line is connected to the ground line circuit for receiving the half-sector ground line signal which is at a predetermined positive potential during erase. 
Advanced Micro Devices, Inc.
G G
G11C G11C
inventional inventional
Michael A. Lee E. Chung K. Johhny C.
Van Buskirk Cleveland Chang Chen