J.C. Patents
Structure and fabrication method using latch-up implantation for improving latch-up immunity in CMOS fabrication process
A structure and fabrication method using latch-up implantation to improve latch-up immunity in CMOS circuit. The impedance of parasitic SCR conducting path is raised by performing an ion-implantation process on a cathode and an anode of a parasitic SCR which may induce latch-up phenomenon. Thus, the parasitic SCR is thus not easily to be conducted with a higher resistance to noise. Therefore, the latch-up immunity can be improved. In addition, the ion implantation process can be performed to achieve the objective of preventing latch-up effect without consuming more area for layout, thus greatly enhances the flexibility in circuit design.
Industrial Technology Research Institute
H H H
H01L H01L H01L
inventional inventional inventional
Hsin-Chin Jeng-Jie Ming-Dou Chyh-Yih
Jiang Peng Ker Chang