Vista IP Law Group, LLP
Methods, systems, and articles of manufacture for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic design
Disclosed are methods, systems, and articles of manufactures for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic design by identifying rules for a first layer and for second layer(s) adjacent to the first layer, determining one or more sets of grids based on the rules, extending or implementing shapes to terminate at some grids of the one or more sets of grids, and populating the data of the ends of the shapes in the first layer in a data structure. The one or more sets of grids are in direction(s) perpendicular to the routing direction(s) of the first layer and have one or more grid pitches determined based at least in part upon routing pitch(es) of the second layer(s) and rule(s) for vias.
Cadence Design Systems, Inc.
G
G06F
inventional
Yuan Jing Shuo Vassilios Jianmin Stefanus
Huang Chen Zhang Gerousis Li Mantik