Merchant & Gould P.C.
Voltage controlled delay line gain calibration
A delay-locked loop includes a phase detector configured to detect a phase difference between a first clock and a second clock, a charge pump configured to increase a charge amount at a capacitive load in accordance with a first charge amount and decrease the charge amount at the capacitive load in accordance with a second charge amount based on a phase difference provided by the phase detector, a sample and hold circuit configured to receive the charge amount from the capacitive load and hold the charge amount, and a voltage control delay line configured to select a delay amount based on the charge amount received from the sample and hold circuit. At least one parameter of the delay-locked loop is configured such that a desired pump current ratio of a delay cell is achieved by adjusting a delay amount of the delay cell and/or an amount of current coupled to the delay cell.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
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Mao-Hsuan Ruey-Bin Chih-Hsien Ya-Tin
Chou Sheen Chang Chang