High speed carbon nanotube memory
In order to realize high speed carbon nanotube memory, bit line is multi-divided into short lines for reducing parasitic capacitance. For reading, a small local sense amp is composed of a local pre amplifier and a local main amplifier with high gain, and a simple global sense amp is composed of an inverter as amplifying circuit for receiving an output of the local sense amp through a global bit line. By the sense amps, time domain sensing scheme is realized such that a voltage difference in the bit line is converted to a time difference as an output of the global sense amp, for differentiating high data and low data. In this manner, fast read operation is realized with fast sensing circuit. And alternative circuits are described. Particularly, field-effect alignment process is realized for aligning the carbon nanotubes on exact location of the memory cell, when forming the memory cell.
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Juhan
Kim