Oliff PLC
Manufacturing method for layered chip packages
In a manufacturing method for layered chip packages, a layered substructure with at least one additional package joined thereto is used to produce a plurality of layered chip packages. The layered substructure includes a plurality of main bodies to be separated from each other later. Each main body includes: a main part having top and bottom surfaces and including a plurality of layer portions stacked on each other; and a plurality of main terminals disposed on at least one of the top and bottom surfaces of the main part. The additional package includes an additional semiconductor chip and at least one additional terminal that is electrically connected to the additional semiconductor chip and in contact with at least one of the plurality of main terminals.
Headway Technologies, Inc. SAE Magnetics (H.K.) Ltd.
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Atsushi Hiroyuki Ryuji Yoshitaka
Iijima Ito Fujii Sasaki