Myers, Bigel & Sibley, P.A.
Semiconductor memory device that controls refresh period, memory system and operating method thereof
A semiconductor memory device includes a cell array and a refresh controller coupled to the cell array. The refresh controller is configured to insert at least one insertion refresh address in a first refresh address sequence based on address information about the cell array to generate a second refresh address sequence and to apply the second refresh address sequence to the cell array, such that selected cells may be refreshed more frequently without increasing an overall refresh rate.
Samsung Electronics Co., Ltd.
G G G G G G G
G11C G11C G11C G11C G11C G11C G11C
inventional inventional additional inventional inventional inventional inventional
Cheol Sang-ho Jung-sik
Kim Shin Kim