Patterns for routing nets in a programmable logic device
Nets of a logic design are efficiently routed in a programmable logic device, which includes multiple types of programmable interconnects. Patterns are read from a library in a storage device. Each pattern includes an ordered set of the types of the programmable interconnects. A path is determined from the source to the destination for each net of the logic design. The path is through a sequence of the programmable interconnects having types that correspond to each type in the ordered set of a selected pattern. A description is output of the path for each of the nets.
Xilinx, Inc.
G
G06F
inventional
Anirban Sandor S. Jason H. Hui Vinay
Rahut Kalman Anderson Xu Verma