Breakdown-free high voltage input circuitry
 A high voltage input circuit includes a triple-well NMOS for reducing the voltage stress across its drain junction for preventing it from breakdown. The triple-well NMOS is fabricated in a P-well formed in a deep N-well on a P-substrate. The P-well is coupled to a power supply voltage by a P-well voltage control device to reduce the voltage difference across the drain junction. A low voltage signal input circuit portion is also added to the high voltage input circuit to allow a high voltage input pin to receive other signal and reduce the total pin count of an integrated circuit. A dual-input buffer such as NAND gate instead of an inverter is used in the low voltage signal input circuit for reducing the voltage stress to the devices in the low voltage signal input circuit. 
Aplus Flash Technology, Inc.
G
G05F
inventional
Hsing-Ya Hung-Sheng Fu-Chang Vei-Han Peter Wung
Tsao Chen Hsu Chan Lee