Eschweiler & Associates, LLC
Multi-patterning conflict free integrated circuit design
The present disclosure relates to a method and apparatus for forming a multiple patterning lithograph (MPL) compliant integrated circuit layout by operating a construction validation check on unassembled IC cells to enforce design restrictions that prevent MPL conflicts after assembly. In some embodiments, the method is performed by generating a plurality of unassembled integrated circuit (IC) cells having a multiple patterning design layer. A construction validation check is performed on the unassembled IC cells to identify violating IC cells having shapes disposed in patterns comprising potential multiple patterning coloring conflicts. Design shapes within a violating IC cell are adjusted to achieve a plurality of violation free IC cells. The plurality of violation free IC cells are then assembled to form an MPL compliant IC layout. Since the MPL compliant IC layout is free of coloring conflicts, a decomposition algorithm can be operated without performing a post assembly color conflict check.
Taiwan Semiconductor Manufacturing Co., Ltd.
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Wen-Li Ken-Hsien Wen-Ju Tsong-Hua Ting Yu Ching Hsiang Yi-Kan Li-Chun Hung Lung Chien Lin Chin-Chang
Cheng Hsieh Yang Ou Chen Chang Cheng Tien Lin Ho Hsu