Method for forming dual-gate CMOS for dynamic random access memory
 A method for forming a dual-gate transistor includes the step of forming a gate oxide layer (18) over two transistor regions provided by a P-tank (12) and an N-tank (14). This is followed by depositing a layer of in-situ doped poly (20) and then masking off a portion of the poly layer (20) overlying the P-tank (12). This is then followed by diffusion of P-type impurities into the portion of the poly layer (20) overlying the N-tank (14) associated with the P-channel transistor. This is a process required for forming a DRAM memory. Utilizing the same oxide mask (22), a threshold implant is formed into the N-type (14). 
Texas Instruments Incorporated
H C
H01L C07H
inventional inventional
Jiann
Liu