Staas & Halsey
Semiconductor memory and method of writing, reading, and sustaining data thereof
 A semiconductor memory has bit lines, word lines, ground lines, and memory cells. The bit lines intersect the word and ground lines, to form intersections where the memory cells are arranged, respectively. Each of the memory cells consists of a double-emitter resonance-tunnel-hot-electron transistor. This transistor has a collector, a first emitter, and a second emitter. Each base-emitter junction of the transistor has an N-shaped negative differential current-voltage characteristic that shows a relatively small gain up to a peak current and a relatively large gain after a valley current. The transistor has a resonance tunnel barrier and a collector barrier so that most of electrons injected from a first level are reflected by the collector barrier, to provide no collector current, and electrons from a second level or electrons thermally excited pass over the collector barrier, to provide a collector current. The first emitter of each transistor is connected to a corresponding one of the ground lines. The second emitter is connected to a corresponding one of the word lines. The collector is connected to a corresponding one of the bit lines. Each of the memory cells has a small number of elements and needs only a small area. 
Fujitsu Limited
G H G
G11C H01L G11C
inventional inventional additional
Toshihiko
Mori