Haynes and Boone, LLP
Dual channel gate all around transistor device and fabrication methods thereof
A method that includes forming first semiconductor layers and second semiconductor layers disposed over a substrate, wherein the first and second semiconductor layers have different material compositions, are alternatingly disposed, and extend over first and second regions of the substrate; patterning the first and the second semiconductor layers to form a first fin in the first region and a second fin in the second region; removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin; forming third semiconductor layers on the second suspended nanostructures in the second fin; and performing an anneal process to drive materials contained in the third semiconductor layers into corresponding second suspended nanostructures in the second fin.
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
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Chih-Hao Chih-Chao Chun-Hsiung Kuo-Cheng Jui-Chien Pei-Hsun
Wang Chou Lin Chiang Huang Wang