Slater & Matsil, L.L.P.
Method for fabricating low-k dielectric and Cu interconnect
A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.
Taiwan Semiconductor Manufacturing Company, Ltd.
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inventional inventional inventional
Chih-Hao Ming-Chung Tzu-Li Chia-Cheng Keng-Chu
Chen Liang Lee Chou Lin