J. C. Patent
Method of forming transistor gate
A method of forming a transistor gate. A substrate having a source/drain terminals, a gate dielectric layer, a lower section of a floating gate, a dielectric layer over the substrate is provided. The dielectric layer has an opening that exposes a portion of the upper surface of the lower section of the floating gate. A conductive material layer having slant exterior sidewalls is formed over the dielectric layer. The conductive material layer fills the via opening completely. A mask material layer is formed over the conductive layer. A mask material layer is formed over the conductive layer. A planarization is carried out to remove a portion of the mask material layer, thereby forming an etching mask layer that exposes the upper surface of the conductive layer. Using the etching mask layer as a mask, an anisotropic slant etching is carried out to etch the conductive layer to a predefined depth so that an opening in the upper section of the floating gate is formed. The etching mask layer is then removed. An inter-gate dielectric layer and a control gate layer are sequentially formed over the upper section of the floating gate to form a complete gate structure.
Macronix International Co., Ltd.
H H
H01L H01L
inventional inventional
Ching-Yu
Chang