Method of forming thin polygates for sub quarter micron CMOS process
 A method is provided for forming thin polysilicon transistor gates using dual doped polysilicon without reducing the ion implant energy. The method comprises depositing polysilicon over a region of a substrate, masking and implanting the polysilicon with dopant impurities to form the channel regions of one conductivity type, and removing the photo resist mask. The polysilicon layer is then masked to define the channel regions of the opposite conductivity type and is implanted with dopant impurities of the opposite conductivity type. Following the dual ion implantation, the photo resist mask is removed and the substrate may be annealed to activate the dopants in the polysilicon. The dual doped polysilicon layer is then polished using a chemical-mechanical polish to achieve a desired thickness for the polysilicon transistor gates. The polysilicon is subsequently masked and etched to define the polysilicon transistor gates. 
LSI Logic Corporation
H
H01L
inventional
Subramanian Ruggero Yauh-Ching Gary
Ramesh Castagnetti Liu Giust