Eschweiler & Associates, LLC
Methodology for pattern density optimization
The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.
Taiwan Semiconductor Manufacturing Co., Ltd.
G G
G03F G06F
inventional inventional
Wen-Chun Cheng-Kun Ping-Chieh Wen-Hao Ru-Gun Hung-Chun Chun-Hung Ming-Hui Cheng-Hsuan
Huang Tsai Wu Liu Liu Wang Wu Chih Huang