Haynes and Boone, LLP
Programmable self-test for random access memories
A system that provides large instruction sets for testing memory yet reduces area overhead is disclosed. The system for testing a memory of an integrated circuit comprises a set of registers providing element based programmability for a plurality of tests, wherein each test includes a plurality of test elements; a finite state machine for receiving a plurality of test instructions from the set of registers, wherein the finite state machine dispatches signals instructing a test pattern generator to generate a test pattern; a memory control module for applying the generated test pattern to the memory; and a comparator module for comparing a response received from the memory to a stored, known response.
Taiwan Semiconductor Manufacturing Company, Ltd.
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G11C G11C
additional inventional
Chingwen Wei-Chia Shih-Chieh
Chang Cheng Lin