Myers Bigel & Sibley, P.A.
Semiconductor packages including gap in interconnection terminals and methods of manufacturing the same
A semiconductor package includes a lower package comprising a lower semiconductor chip mounted on a lower package substrate, an upper package comprising an upper package substrate stacked on the lower package and an upper semiconductor chip mounted on the upper package substrate, interconnection terminals electrically connecting the lower package substrate with the upper package substrate, and a lower molding film molding the lower semiconductor chip between the lower package substrate and the upper package substrate. The lower package substrate comprises a chip region on which the lower semiconductor chip is mounted, an interconnection region enclosing a portion of the chip region, and a mold injection region defined by the chip region and the interconnection region. The interconnection terminals are disposed on the lower package substrate of the interconnection region but not disposed on the lower package substrate of the mold injection region.
Samsung Electronics Co., Ltd.
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inventional inventional inventional inventional additional additional inventional additional additional inventional additional additional additional additional inventional inventional additional additional inventional additional inventional inventional inventional additional additional additional additional inventional
Jungwoo Jingyu
Kim Kim