Conley Rose P.C.
Equalization time configuration method, chip, and communications system
An equalization time configuration method, applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used, includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.
HUAWEI TECHNOLOGIES CO., LTD.
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Jiang Yulong Yongyao Jiankang Fei
Zhu Ma Li Li Luo