Eschweiler & Potashnik, LLC
Method for forming a flat bottom electrode via (BEVA) top surface for memory
Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
Taiwan Semiconductor Manufacturing Company, Ltd.
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I-Ching Chih-Yang Chin-Chieh Yu-Wen Sheng-Hung Hsia-Wei Wen-Ting Tung-Sheng Jen-Sheng
Chen Chang Yang Liao Shih Chen Chu Hsiao Yang