Cantor Colburn LLP
Vertical transistor having reduced edge fin variation
A semiconductor device includes a substrate with a first semiconductor fin and a second semiconductor fin formed thereon. A pair of opposing dielectric trench spacers are between the first and second semiconductor fins. The opposing dielectric trench spacers define an isolation region therebetween. The semiconductor device further includes a shallow trench isolation (STI) element formed in the isolation region. The STI element includes a lower portion on the substrate and an upper portion located opposite the lower portion. The upper portion extends above an upper end of the dielectric trench spacers.
INTERNATIONAL BUSINESS MACHINES CORPORATION
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Zhenxing Dexin Juntao Kangguo
Bi Kong Li Cheng