Finnegan, Henderson, Farabow & Garrett
Counter using an inverter and shift registers
 A counter comprises a cascade connection of an inverter stage and n one-bit shift register stages, the latter being operative in response to clock signals to be counted and each having a data-readin or front half-bit shift register stage and a data-readout or rear half-bit shift register stage. The output of the final stage in the cascade connection is coupled to the input of the first stage in the cascade connection. The output of the final stage is also coupled to an additional input of consecutive 1st to X-th shift register stages or consecutive 2nd to (X-1)-th shift register stages of an X-th shift register stage to constitute a scale-of-2n-X or 2n-(X-1) counter. 
Tokyo Shibaura Electric Co., Ltd.
H G H
H03K G11C H03K
inventional inventional inventional
Masataka Yasoji Kenshi
Hirasawa Suzuki Manabe