Glitch-free clock generator and method for generating glitch-free clock signal
A clock generator that generates an output clock signal, includes a clock generating circuit that generates an internal clock signal, first and second filter circuits, and an output gate. The first filter circuit receives the internal clock signal and an enable signal, and provides a first filtered enable signal in response to the enable signal having a duration of at least two cycles of the clock signal. The second filter circuit receives the first filtered enable signal, provides a second filtered enable signal in response to the first filtered enable signal, and provides a delayed signal that is a delayed version of the second filtered enable signal. The output gate receives the internal clock signal from the clock generating circuit and the second filtered enable signal from the second filter circuit, and generates the output clock signal.
NXP USA, Inc.
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Jianluo Hongyan Yan Bin
Chen Yao Huang Zhang