Merchant, Gould, Smith, Edell, Welter and Schmidt
Method for manufacturing an MOS transistor having a self-aligned and planarized raised source/drain structure
 A new method for manufacturing an MOS transistor is applied in the deep submicron process. In this method, a polysilicon layer is mainly used to form a raised source/drain structure and self-alignment is achieved by means of a planarization process. This method can reduce short channel effects and the series impedance of the source/drain as well as accomplish the local interconnection of a circuit and planarization. Therefore, this method is very suitable for manufacturing devices in the deep submicron process. 
National Science Council
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inventional additional inventional inventional additional
Tiao-yuan Horng-Chih
Huang Lin