Ladas & Parry LLP
Algorithm analog-to-digital converter
Provided is an algorithm analog-to-digital converter (ADC). The algorithm ADC obtains two digital outputs through different capacitor connections for one analog input signal and adds the digital output signals to obtain a final output value, so that a mismatch factor of the capacitor is removed to minimize a linearity limitation resulting from the capacitor mismatch. In addition, the algorithm ADC minimizes power consumption by making the operating frequency slow at a cycle requiring a high resolution and making the operating frequency fast at a cycle requiring a low resolution, i.e., outputting different operating clock frequencies according to a required resolution.
Electronics and Telecommunications Research Institute
H H
H03M H03M
inventional additional
Seung Chul Kwi Dong Young Deuk Jong Kee
Lee Kim Jeon Kwon