Kowert, Hood, Munyon, Rankin & Goetzel, P.C.
Divider control and reset for phase-locked loops
In a computer system, a phase-locked loop circuit may generate a clock signal using a reference signal. The phase-locked loop circuit may include a programmable divider stage that includes multiple divider stages. When a frequency calibration is initiated on the phase-locked loop circuit, a control circuit may generate a pause signal in response to one or more of the divider stages reaching a particular logic state. The programmable divider stage may hold the one or more of the divider stages in the particular logic state using the pause signal.
Apple Inc.
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Cristian Chunwei Robert K. Saeed Wei Feng
Marcu Chang Kong Chehrazi Deng Zhao