Schwabe, Williamson & Wyatt, P.C.
Aspect ratio trapping (ART) for fabricating vertical semiconductor devices
Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.
Intel Corporation
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Jack T. Marko Niloy Van H. Ravi Matthew V. Benjamin Gilbert Robert S. Willy
Kavalieros Radosavljevic Mukherjee Le Pillarisetty Metz Chu-Kung Dewey Chau Rachmady