Haynes and Boone, LLP
Memory circuit and cache circuit configuration
A method of operating a memory circuit is disclosed. The memory circuit comprises a primary memory and a cache memory. The primary memory has P access channels of Q bits of channel bandwidth, and the cache memory has P subsets of Q*N memory cells, wherein P and Q are integers greater than 1, and N is a positive integer. The method includes determining, in response to a command for reading first and second data accessible through first and second access channels respectively, if a valid duplication of the first and second data is stored in the cache memory. If yes, the method further includes storing a duplication of Q*n bits of consecutively addressed data from each of the first and second access channels to the cache memory, n being an integer from 1 to N. Otherwise, the method further includes outputting the first and second data from the cache memory.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
G G G G G G G G H G H
G11C G06F G11C G06F G06F G06F G06F G06F H01L G11C H01L
inventional additional inventional additional additional additional inventional inventional additional inventional additional
Hsien-Hsin Sean Yun-Han William Wu
Lee Lee Shen