Sughrue, Mion, Zinn, Macpeak & Seas, PLLC
Semiconductor substrate with SOI structure
 A semiconductor substrate which is optimum for a substrate for integrating a vertical power element and a control circuit element monolithically. A cavity 3 is formed between a dielectric layer 2 and a single crystal silicon substrate 4 in a control circuit element forming region 8, and junction planes 1a and 4a of single crystal silicon substrates 1 and 4 are joined together. Since bonding of regions where a vertical power element is formed is made with flat single crystal silicon planes, no void (non-bonded portion) is generated on the junction plane of the region where the vertical power element is formed. As a result, it is possible to realize a semiconductor device provided with perfect junction having electrical conductivity in a direction perpendicular to the junction interface. 
NEC Corporation
H H H
H01L H01L H01L
inventional additional additional
Kenichi Hiroaki
Arai Kikuchi