Configurable cache system depending on instruction type
A processor comprises decode logic that determines an instruction type for each instruction fetched, a first level cache, a second level cache coupled to the first level cache, and control logic operatively coupled to the first and second level caches. The control logic preferably causes cache linefills to be performed to the first level cache upon cache misses for a first type of instruction, but precludes linefills from being performed to the first level cache for a second type of instruction.
Texas Instruments Incorporated
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inventional inventional inventional additional additional inventional inventional
Paul K. Muralidharan S. Raul A. Thang M.
Miller Chinnakonda Garibay, Jr. Tran