Oliff & Berridge, PLC
Layered chip package with wiring on the side surfaces
A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include specific pairs of layer portions. Each of the specific pairs of layer portions includes a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. The specific pairs of layer portions are provided in an even number.
Headway Technologies, Inc. SAE Magnetics (H.K.) Ltd. TDK Corporation
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Tatsuya Nobuyuki Hiroyuki Hiroshi Yoshitaka Satoru
Harada Okuzawa Ito Ikejima Sasaki Sueki