J.C. Patents
Circuit for computing sums of absolute difference
A circuit for computing sums of absolute difference (SAD) is provided. The circuit has an absolute difference circuit, a first adder, a first register and a first selective circuit. The absolute difference circuit receives a first data PMi,j and a second data PSi,j and output a absolute difference data ADi,j, wherein ADi,j=|PMi,j−PSi,j|. The first adder receives and adds the absolute difference data and a first accumulative data, and outputs a first sum. The register receives and locks the first sum according to a first preset timing sequence, and outputs a first sum of absolute difference data. The first selective circuit receives and selects the first sum of absolute difference data or 0, and outputs the selected data as the first accumulative data.
Novatek Microelectronics Corp.
G H G
G06F H04N G06F
inventional inventional additional
Jin-Ming Hsing-Chien Hsing-Chien
Chen Lucian-Yuan Yang