Baker Botts L.L.P.
Analyzing substrate noise
In one embodiment, a method for analyzing substrate noise includes applying a static timing analysis (STA) algorithm to a description of a digital circuit. Application of the STA algorithm generates timing information on one or more gates in the digital circuit. The method also includes applying a current waveform generation (CWG) algorithm to the description of the digital circuit, the timing information on one or more gates in the digital circuit, and a description of switching activity in the digital circuit. Application of the CWG algorithm generates a current waveform. The method also includes generating a reduced model (RM) of the digital circuit for simulation according to the description of the digital circuit, the current waveform, and a model of a package associated with the digital circuit. Simulation of the RM of the digital circuit generates an indication of noise in a substrate associated with the digital circuit.
Fujitsu Limited
G
G06F
inventional
Subodh M. Mehdi B. Takeshi Takashi Rajeev
Reddy Tahoori Horie Miyoshi Murgai