Staas & Halsey
ECL latch circuit having a noise resistance circuit in only one feedback path
 A latch circuit including at least three gate circuits, and a noise resistance circuit. A first gate circuit (3, 4, 11, 16) receives a data signal (DT) and a clock signal (CLK). A second gate circuit (1, 7, 13, 17) is connected to an output of the first gate circuit. A third gate circuit (2, 5, 12 18) receives a first inverted clock signal (CLK) at an input terminal. A second input terminal of the third gate circuit is connected to an output of the second gate circuit and is a first output terminal is connected to an input terminal of the second gate circuit, so that a feedback line is formed between the second and third gate circuits. The noise resistance circuit (8, 9, 20, 21) has at least a signal delay element in the feedback line. The noise resistance circuit may include a filter circuit. The noise resistance circuit may also include an amplifier circuit. 
Fujitsu Limited
H H
H03K H03K
inventional inventional
Mitsuhisa Kazumasa Taichi Toshiaki Yasunori Hiroki
Shimizu Nawata Saitoh Sakai Kanai Yada