Volentine Francos, PLLC
Semiconductor memory device having memory cell array structure with improved bit line precharge time and method thereof
A semiconductor memory device having a memory cell array structure and a precharging method, that improves bit line precharge time. The device has a common sense amplifier structure and includes memory cell blocks, first and second sense amplifiers and a dummy capacitor region. The first sense amplifier is arranged between and is shared by two adjacent memory cell blocks, to sense and detect data of memory cells. The second sense amplifier is connected to a memory cell block at an edge of the array structure, to sense and detect memory cell data. The dummy capacitor region includes capacitors between a dummy bit line and a complementary dummy bit line which are connected to the bit line and complementary bit line of the memory cell block at the edge of the array structure. The capacitors have a capacitance substantially equal to line capacitance of the bit line.
Samsung Electronics Co., Ltd.
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inventional inventional inventional
Seung-hoon
Lee