Fenwick & West
Interleave technique for accessing digital memory
 An electronic storage circuit includes a pair of banks, each bank having corresponding shared and unshared conductors. The banks may be dynamic random access memories (DRAMs), which are provided in a single inline memory module (SIMM). Each DRAM includes an array of bit cells arranged in rows and columns. A shared conductor of one bank is connected to the unshared conductor of the other bank, and the unshared conductor of such one bank is connected to the shared conductor of such other bank. Row and column address signals are applicable to the connections between the banks, thereby allowing selectable access (or write) to the banks. Each bank includes corresponding data and output enable conductors, such that in response to output enable signals applied to such output enable conductors, data signals are generated by corresponding banks at the data conductors, depending on the state of the applied address signals. 
ShaBLAMM! Computer Inc.
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G06F G11C
inventional inventional
Tom Francis
North Siu