Multi-finger input buffer with transistor gates capacitively coupled to ground
 An input buffer for a CMOS integrated circuit comprises parallel pairs of complementary PMOS pull-up and NMOS pull-down transistors. Floating NMOS gates are capacitively coupled to V.sub.SS by a first-level metalization pattern. The metal-to-gate overlap capacitance and the gate-to-drain overlap capacitance define a voltage divider that leaves the gate at a small positive voltage during an electrostatic discharge event. This ensures that all NMOS transistors of a buffer enter a conducting bipolar mode before any of them enters second breakdown. This arrangement maximizes input-buffer protection from electrostatic discharge events. The novel NMOS arrangement is readily compatible with gate array designs. 
VLSI Technology, Inc.
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inventional inventional inventional
Tiao-Yuan
Huang