Myers Bigel Sibley & Sajovec
CMOS operational amplifiers having reduced power consumption requirements and improved phase margin characteristics
 Operational amplifier integrated circuits include a differential input stage, a cascode current mirror, a cascode current source and a preferred bias signal generator which is responsive to a clock signal and is electrically coupled to the differential input stage, the cascode current mirror and the cascode current source. This preferred bias signal generator sequentially enables the cascode current mirror and then the differential input stage in response to a rising edge of the clock signal and disables the cascode current mirror and the cascode current source in response to a falling edge of the clock signal. This sequential enablement of the cascode current mirror before the differential input stage improves the unity gain phase margin characteristics of the circuit and the disablement of the cascode current mirror and the cascode current source in response to the falling edge of the clock signal decreases the power consumption requirements of the circuit. 
Samsung Electronics Co., Ltd.
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additional inventional inventional
Geun-Soon Seung-Hoon Hee-Cheol Dong-Young You-Mi
Kang Lee Choi Chang Lee