Christopher P. Maiorana, P.C.
Configurable fast clock detection logic with programmable resolution
An apparatus comprising a first logic circuit and a second logic circuit. The first logic circuit may comprise one or more counters and may be configured to synchronize a plurality of input clock signals. The second logic circuit may be configured to detect and present a faster clock signal of the synchronized clock signals.
Cypress Semiconductor Corp.
G
G06F
inventional
Somnath S. Babar Jiann-Cheng
Paul Raza Chen