Foley & Lardner
Dynamic random access memory device
 Here is disclosed a dynamic semiconductor memory of high integration density, which has parallel word lines and parallel bit lines formed on a substrate. The bit lines include a pair of bit lines. A memory cell is coupled to a word line and to one bit line of the bit-line pair. The memory cell is composed of MOSFETs of a submicron size. A sense amplifier section is connected to the pair of bit lines, and senses and amplifies the potential difference between the pair of bit lines in a data readout mode. The amplifier section has a BIMOS structure, having MOSFETs and bipolar transistors. It has a driver section comprised of bipolar transistors. 
Kabushiki Kaisha Toshiba
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Shigeyoshi Masako Fujio Tsuneaki Kenji Koji Yukihito
Watanabe Ohta Masuoka Fuse Numata Sakui Oowaki