Lowe Hauptman Ham & Berner, LLP
Method for checking and fixing double-patterning layout
A method and system checks a double patterning layout and outputs a representation of G0-rule violations and critical G0-spaces. The method includes receiving layout data having patterns, determining whether each distance between adjacent pattern elements is a G0-space, find all G0-space forming a G0-rule violation, finding all G0-space that are critical G0-spaces, and outputting a representation of G0-rule violations and critical G0-spaces to an output device. By resolving G0-rule violations and critical G0-spaces, a design checker can effectively generate a double patterning technology (DPT) compliant layout.
Taiwan Semiconductor Manufacturing Company, Ltd.
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G06F G21K G06F G03F G06F
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Huang-Yu Li-Chun Lee-Chung Dio Ru-Gun Ken-Hsien
Chen Tien Lu Wang Liu Hsieh