Finnegan, Henderson, Farabow, Garrett & Dunner
Circuit for producing a polarity-reversed voltage with opposite polarity to that of a power supply voltage
 An inverter is controlled by first clock pulses for converting a positive power supply into second clock pulses having a first voltage level of the power supply and a second voltage level of a reference voltage. The second clock pulses are supplied to a capacitor. The source-drain path of a first impedance varying P-FET is connected between the output terminal of the capacitor and the reference voltage and is controlled so as to take a low impedance when the second clock pulses are at the first voltage level while a high impedance when the second clock pulses are at the second voltage level. The source-drain path of a second impedance varying P-FET is connected between the output terminal and a terminal for taking out a polarity-reversed voltage. The second impedance varying P-FET is supplied at the gate with the first clock pulses so as to be controlled to take a high impendance when the second clock pulses are at the first voltage level and a low impedance when the second clock pulses are at the second level. 
Tokyo Shibaura Denki Kabushiki Kaisha
H H
H03K H02M
inventional inventional
Tetsuya Yasoji
Iida Suzuki