Method to reduce contact resistance of N-channel transistors by using a III-V semiconductor interlayer in source and drain
A method to reduce contact resistance of n-channel transistors by using a III-V semiconductor interlayer in source and drain is generally presented. In this regard, a device is introduced comprising an n-type transistor with a source region and a drain region a first interlayer dielectric layer adjacent the transistor, a trench through the first interlayer dielectric layer to the source region, and a conductive source contact in the trench, the source contact being separated from the source region by a III-V semiconductor interlayer. Other embodiments are also disclosed and claimed.
Intel Corporation
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H01L H01L
inventional inventional
Matthew V. Niloy Marko Gilbert Robert S.
Metz Mukherjee Radosavljevic Dewey Chau