Redundant read bus for correcting defective columns in a cache memory
 A cache memory architecture having a separate redundant read bus fully dedicated to redundancy and fed by a single spare sub-array common to all memory sub-arrays of the cache memory. Redundant sense amplifiers are dotted to the redundant read bus, and normal sense amplifiers are connected to a main read bus. Normal and redundant data are valid and available at the same time at the outputs of the normal and redundant sense amplifiers. When the late select address signals become valid, then the correct information can be selected via a multiplexer provided with an INHIBIT input. The multiplexer is normally controlled by decoded signals generated by a decoder, unless redundancy is required. If redundancy is required, the information generated by the bit address comparator forces the multiplexer, via the INHIBIT input, to select the redundant read bus, instead of one read bus of the main read bus, and to output the redundant byte as the selected one. 
International Business Machines Corporation
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inventional inventional inventional inventional
Philippe Bertrand Dominique
Girard Gabillard Omet