Volentine & Whitt, PLLC
Delay cell, delay locked look circuit, and phase locked loop circuit
A delay cell includes a first transistor and a second transistor, at least one of which has a fully depleted silicon-on-insulator (FD-SOI) structure. A first control voltage is applied to the body of the first transistor and a second control voltage is applied to the body of the second transistors in order to adjust the delay time of the delay cell. DLL and PLL circuits includes this type of delay cell.
Samsung Electronics Co., Ltd.
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inventional inventional additional inventional
Dong-Hyuk Seung-Hoon Jae-Jin
Lim Lee Park