Marshall, Gerstein & Borun LLP
Circuit for generating column selection control signal in memory device
A circuit for generating a Yi control signal in a memory device. The circuit comprises a column select signal control block for generating a Yi control signal for a normal operation of a first cycle of a page mode, a latch for setting the Yi control signal from the column select signal control block, a read reset block for resetting the latch, a page read Yi enable block for generating the Yi control signal when a page address is changed in a page read mode and then setting the latch, and a page read reset block for resetting the latch set by the page read Yi enable block.
Hynix Semiconductor, Inc.
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Jung Kyun
Choi