Vierra Magen Marcus Harmon & DeNiro LLP
Input/output circuit with on-chip inductor to reduce parasitic capacitance
An I/O circuit disposed on an integrated circuit substrate and having reduced parasitic capacitance. The I/O circuit includes a signal line segmented into a first signal line segment and a second signal line segment, and an inductive structure disposed between the first and second signal line segments. An on-chip termination element is coupled to the first signal line segment, and an electrostatic discharge (ESD) element is coupled to the second signal line segment.
Rambus Inc.
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Pak S. Vladimir M. Mark A. Jared L.
Chau Stojanovic Horowitz Zerbe