Hamilton & Terrile, LLP
High pressure deuterium treatment for semiconductor/high-K insulator interface
An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.
Freescale Semiconductor, Inc.
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Dae-Gyu Laegu Melanie J. Weipeng Xiangdong
Park Kang Sherony Li Chen