Marshall, Gerstein & Borun LLP
Method for manufacturing a capacitor lower electrode over a transistor and a bit line corresponding to a cell area of a semiconductor device
Disclosed is method for manufacturing a semiconductor device, wherein a photosensitive layer and a natural oxidation layer on a cell area and a peripheral circuit area are removed by dry etching while a capacitor of a DRAM device is manufactured, and a polysilicon layer which is not used in the following process is removed by controlling the composition ratio of CF4 gas and O2 gas and the change of pressure and electrical power in two steps so as to reduce the etching selection ratio of the photosensitive layer and the natural oxidation layer with respect to the polysilicon, whereby the remaining polysilicon is prevented regardless of the etching time and etching amount.
Hynix Semiconductor Inc
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Jin-ho Sang-ryong Ki-won Jung-guk
Park Oh Nam Kim