Panasonic IP Management
Semiconductor device having stacked chips, a re-distribution layer, and penetration electrodes
A lamination structure includes a first semiconductor chip and a second semiconductor chip stacked via a bonding section so that a rear surface of the first semiconductor chip faces the main surface of the second semiconductor chip. At least a part of a side surface of the first semiconductor chip are covered with a first resin, a distribution layer is formed on the plane formed of the main surface of the first semiconductor chip and a surface of the first resin. At least part of electrodes existing in the main surface of the second semiconductor chip is electrically connected to at least part of first external electrodes formed on the distribution layer via the penetration electrodes that penetrate the first semiconductor chip.
Panasonic Corporation
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additional inventional additional additional additional additional inventional additional additional inventional inventional additional additional inventional additional additional inventional inventional inventional additional additional additional additional inventional inventional inventional additional additional additional additional additional additional additional inventional additional additional additional additional additional additional
Nobuo Toshio Masaru Takeshi Takashi Yoshihiro
Aoi Fujii Sasago Kawabata Yui Mori