Oliff & Berridge, PLC
Method of manufacturing layered chip package
A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body. Each substructure is fabricated through the steps of: fabricating a pre-substructure wafer including a plurality of pre-semiconductor-chip portions aligned; distinguishing between a normally functioning pre-semiconductor-chip portion and a malfunctioning pre-semiconductor-chip portion among the plurality of pre-semiconductor-chip portions included in the pre-substructure wafer; and forming electrodes connected to the normally functioning pre-semiconductor-chip portion and having respective end faces located in the side surface of the main body on which the wiring is disposed, without forming any electrode connected to the malfunctioning pre-semiconductor-chip portion.
Headway Technologies, Inc. SAE Magnetics (H.K.) Ltd. TDK Corporation
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Nobuyuki Hiroshi Tatsuya Hiroyuki Yoshitaka Satoru
Okuzawa Ikejima Harada Ito Sasaki Sueki