Dynamic memory rank configuration
Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.
Rambus Inc.
G G G G G H G
G11C G11C G11C G11C G11C H01L G11C
inventional inventional inventional additional inventional additional inventional
Gary B. Brent S. Fariborz Mark D. Mark A.
Bronner Haukness Assaderaghi Kellam Horowitz