Davis Wright Tremaine LLP
Charge cycling by equalizing the source and bit line levels between pulses during no-verify write operations for NAND flash memory
In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. In some cases a non-volatile memory is programmed by an alternating set of pulses, but, for at least some pulses without any intervening verify operations. After a one pulse, but before biasing the memory for the next pulse without an intervening very, the source and bit line levels can be left to float.
SanDisk Technologies Inc.
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inventional inventional additional
Juan Carlos Jongmin Man Lung Hao Thai Seungpil
Lee Park Mui Nguyen Lee