High current and/or high speed electrically erasable memory cell for programmable logic devices
An electrically erasable programmable logic device (EEPLD) cell (100) is disclosed. A folded floating gate (110) and folded select gate (108) can form two parallel read current paths (Isense0 and Isense1). A first read current path (Isense0) may be formed between a first semiconductor region (104) and a second semiconductor region (106-0), and may be controlled by a first floating gate portion (110-0) and a first select gate portion (108-0). A second read current path (Isense1) may be formed between the first semiconductor region (104) and a third semiconductor region (106-1) that is coupled to a second semiconductor region (106-0). A second read current path (Isense1) may be controlled by a second floating gate portion (110-1) and a second select gate portion (108-1).
Cypress Semiconductor Corporation
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H01L H01L G11C H01L
inventional inventional additional inventional
Kevin Yue Sheng-Yueh
Yen Chen Pai