Slater Matsil, LLP
Methods for double-patterning-compliant standard cell design
A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
Taiwan Semiconductor Manufacturing Company, Ltd.
H G H H H
H01L G06F H01L H01L H01L
inventional inventional additional additional additional
Gwan Sin Yi-Kan Huang-Yu Li-Chun Fung Song Lee-Chung Yuan-Te Wen-Ju
Chang Cheng Chen Tien Lee Lu Hou Yang