Cooper Legal Group, LLC
Phase-locked loop (PLL)
A phase-locked loop (PLL) is provided. The PLL comprises a clock adjuster configured to receive an initial clock signal having an initial frequency and a mode control signal. The clock adjuster is configured to modify the initial clock signal into a modified clock signal based on the mode control signal. The PLL is configured such that a loop bandwidth is equal to a specified bandwidth. When the modified clock signal is changed, a loop gain of a loop filter is adjusted such that the loop bandwidth is substantially equal to the specified bandwidth. When the modified clock signal is changed, an oscillator tuning word (OTW) signal is modified into a normalized OTW signal such that the loop bandwidth is substantially equal to the specified bandwidth.
Taiwan Semiconductor Manufacturing Company Limited
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H03L H03L H03L
inventional inventional additional
Huan-Neng Lee Tsung Feng Wei Kuang-Kai Robert Bogdan Chewn-Pu
Chen Hsiung Kuo Yen Staszewski Jou