Martin & Associates, LLC
Accelerator generation using parallel synthesis and simulation
An accelerator image generator includes a synthesis block and a simulation block. The accelerator image generator receives a hardware description language representation for a desired function, inputs the hardware description language representation for the desired function to the synthesis block and to the simulation block so the synthesis block and simulation block work in parallel, monitors progress of the synthesis block and the simulation block, and when a defined threshold is reached in the synthesis block, halts the simulation block while the synthesis block continues until the synthesis block outputs an accelerator image for deployment to a programmable device. When an error is detected in the synthesis block following halting of the simulation block, the simulation block may be resumed, and the defined threshold may be adjusted. The accelerator image can be deployed to a programmable device to provide a hardware accelerator corresponding to the accelerator image.
International Business Machines Corporation
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Lance G. Jim C. James E. Paul E.
Thompson Chen Carey Schardt