Myers Bigel Sibley & Sajovec, P.A.
Resistive memory devices having a stacked structure and methods of operation thereof
A memory device includes a stacked resistive memory cell array comprising a plurality of resistive memory cell layers stacked on a semiconductor substrate, wherein respective memory cell layers are configured to store data according to respective program modes comprising a number of bits per cell. The memory device further includes a control circuit configured to identify a program mode of a selected memory cell layer responsive to an address signal and to access the selected memory cell layer responsive to the address signal according to the identified program mode. The program modes may include a single-level cell mode and at least one multi-level cell mode.
Samsung Electronics Co., Ltd.
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Sang Beom Chul Woo Hyun Ho Ho Jung
Kang Park Choi Kim