Muir Patent Law, PLLC
Semiconductor memory device having resistive memory cells and method of testing the same
A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set.
SAMSUNG ELECTRONICS CO., LTD.
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Hyung-Rok Hye-Jin Sang-Beom Dong-Seok Yun-Sang Dong-Hyun Chul-Woo
Oh Kim Kang Kang Lee Sohn Park