Transistor structure with stress modification and capacitive reduction feature in a width direction and method thereof
A transistor comprises a source and drain positioned within an active region. A gate overlies a channel area of the active region, wherein the channel region separates the source and drain. The transistor further comprises at least one stress modifier and capacitive reduction feature extending from the source to the drain and underlying the gate for reducing capacitance associated with the gate, source and drain. The at least one stress modifier and capacitive reduction feature comprises dielectric and includes a shape defined at least partially by the active region.
Freescale Semiconductor, Inc.
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Michael A. Vance H. Jian Choh-Fei Venkat R.
Mendicino Adams Chen Yeap Kolagunta