Cesari & Reed, LLP
MISO equalization with ADC averaging
An apparatus may include a circuit configured to generate a set of first ADC samples based on a first signal associated with a first read head position and a failed segment and to generate a set of second ADC samples based on a second signal associated with a second read head position and the failed segment. The circuit may then generate, by a MISO equalizer, a set of equalized ADC samples based on the set of first ADC samples and the set of second ADC samples.
Seagate Technology LLC
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Jason Charles Jason Michael J Marcus
Jury Bellorado Link Marrow