Duane Morris LLP
Phase-locked-loop architecture
A phase-lock-loop (PLL) circuit includes a reference PLL circuit configured to generate a reference clock signal; a single clock tree circuit, coupled to the reference PLL circuit, and configured to distribute the reference clock signal; and a plurality of designated PLL circuits coupled to the clock tree circuit, wherein the designated PLL circuits are each configured to receive the distributed reference clock signal through the single clock tree circuit and provide a respective clock signal based on the reference clock signal.
Taiwan Semiconductor Manufacturing Co., Ltd.
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Chih-Hsien Tsung-Hsien Ruey-Bin
Chang Tsai Shen