Jianq Chyun IP Office
Clock tree in circuit having a power-mode control circuit to determine a first delay time and a second delay time
A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively.
Industrial Technology Research Institute Chung Yuan Christian University National Tsing Hua University
G
G06F
inventional
Chung-Han Yow-Tyng Shih-Chieh Shih-Hsu
Chou Nieh Chang Huang