Myers Bigel Sibley & Sajovec
Methods of fabricating conductive contacts for integrated circuit memory devices using first and second dielectric layers and first and second conductive layers
 Contacts to a cell area and to a core area of integrated circuit memory devices are fabricated by forming a first interlayer dielectric layer on the cell area and on the core area, including on a plurality of spaced apart insulated gates in the cell area. The first interlayer dielectric layer includes therein a plurality of first contact holes having sidewalls that extend from a face of the first interlayer dielectric layer through the first interlayer dielectric layer. The first contact holes further extend between the plurality of spaced apart insulated gates. A first recessed conductive layer is formed in the plurality of first contact holes, between the plurality of spaced apart insulating gates, and recessed beneath the face of the first interlayer dielectric layer. A second dielectric layer then is conformally formed on the face of the first dielectric layer, on the sidewalls of the first contact holes and on the first recessed conductive layer in the first contact holes. At least a portion of the second dielectric layer is removed from on the first recessed conductive layer. A second conductive layer is formed in the first contact holes between the second dielectric layer on the sidewalls of the first contact holes. Thus, high aspect ratio contacts to the cell area may be provided. Second contact holes then may be formed in the core area, extending through the second dielectric layer and the first dielectric layer. A third conductive layer then may be conformally formed on the second dielectric layer, on the second conductive layer and lining the second contact holes. Thus, conductive contacts for the core area and the cell area may be formed simultaneously. 
Samsung Electronics Co., Ltd.
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Yun Gi
Kim