Lowenstein Sandler LLP
Handling bad blocks generated during a block erase operation
A memory component includes multiple fuses, a memory array having a multiple blocks, and control logic operatively coupled with the memory array and the plurality of fuses. The control logic is to receive an erase command associated with the memory array and attempt to erase, in response to receipt of the erase command, a block of the multiple blocks from the memory array. The control logic is further to detect a failure to completely erase the block. The control logic is further to receive a blow fuse command in response to the failure to completely erase the block. The control logic is to blow a fuse, of the multiple fuses, which is coupled with the block, to make the block of the multiple blocks inaccessible to the control logic.
Micron Technology, Inc.
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Daniel J. Kevin R. Marc S. William
Hubbard Brandt Hamilton Akin