Foley & Lardner LLP
System and method for in-situ programming and read operation adjustments in a non-volatile memory
A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programming operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.
SANDISK TECHNOLOGIES LLC
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Mohan Piyush Deepanshu Xiang Huai-Yuan Wei
Dunga Dak Dutta Yang Tseng Zhao