Haynes and Boone, LLP
Structure with embedded memory device and contact isolation scheme
The present disclosure provides a method of fabricating an integrated circuit in accordance with some embodiments. The method includes forming a source and a drain on a fin active region of a semiconductor substrate; depositing an interlayer dielectric (ILD) layer on the source and drain; patterning the ILD layer to form a first contact hole and a second contact hole aligning with the source and drain, respectively; forming a dielectric material layer in the first contact hole; and forming a first conductive feature and a second conductive feature in the first and second contact holes, respectively.
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
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inventional inventional additional inventional inventional additional inventional inventional additional inventional additional additional inventional additional inventional inventional inventional inventional inventional additional additional additional inventional inventional inventional inventional inventional
Min-Yann Huang-Kui Fan-Shuen
Hsieh Chen Meng