Lowe, Price, LeBlanc & Becker
Semiconductor memory having internal test circuit
 A random access semiconductor memory having an array of memory cells is provided with an internal test circuit for testing the contents of rows of stored test pattern data which are read from the array in units of data rows, each read from an entire row of cells of the array. The test circuit can be based on a set of transistors which are respectively coupled to the bit lines of the cell array, for detecting coincidence between the states of all of the bits of a data row that is read out, or coincidence between the states of a predetermined set of the row bits. 
Matsushita Electric Industrial Co., Ltd.
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G11C G11C
inventional inventional
Toshiki
Mori