Optimization of S/D annealing to minimize S/D shorts in memory array
 A method for eliminating source/drain shorting generated during the highly-doped source/drain implant steps in a standard STI process is provided. This is achieved by reducing the RTA temperature to be less than 1000.degree. C. so as to minimize enhanced doping diffusion. Further, the energy level for the highly-doped source/drain implant steps is increased so to compensate for poly depletion in the gate electrodes. 
Lattice Semiconductor Corporation
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inventional inventional inventional inventional
Robert H. Xiao-Yu Sunil D. Christopher O.
Tu Li Mehta Schmidt