Tung & Associates
Built-in stress pattern on IC dies and method of forming
 An IC die formed with built-in stress test pattern and a method for forming such pattern are described. The stress test pattern may be formed by first forming a thermal oxide insulation layer on a silicon substrate, then forming a first plurality of diagonally positioned linear metal traces of a first metal, then depositing an electrically insulating material layer on top of the first plurality of diagonally positioned metal traces, and forming a second plurality of L-shaped metal bars of a second metal positioned with the two sides of L parallel to the two sides of a corner region and overlapping the first plurality of metal traces with the electrically insulating material layer therein between. The double metal method for forming the stress test pattern can be easily incorporated into the fabrication process for an IC die without any additional deposition or photolithographic steps. The metal 1 and metal 2 layers may be suitably formed of aluminum or an aluminum alloy, or any other conductive metallic material. The L-shaped metal bars formed by the metal 2 layer should intersect the linear metal traces at a 45.degree. angle with an isolation layer therein between. An electrical resistance between the two metal layers can be determined by a leakage current therein between as a direct indication of the thermo-mechanical stresses, or shear stresses existing between the two metal layers. The present invention stress test pattern can be formed in any size or dimensions as long as one metal layer is formed in linear, diagonal strips while the other metal layer is formed in L-shaped metal bars overlapping the first metal layer. 
Industrial Technology Research Institute
H H
H01L H01L
inventional additional
Chia-Chung Hsin-Chien Chung-Tao
Wang Huang Chang