Jaffery Watson Mendonsa & Hamilton LLP
Optimizing memory address compression
A mechanism is described for facilitating memory address compression at computing devices. A method of embodiments, as described herein, includes coalescing slot addresses across multiple messages received from an execution unit, where the slot addresses are coalesced in groups based on memory cacheline addresses such that each of a set of slot addresses in a group have a memory cacheline address in common between them. The method may further include outputting the memory cacheline addresses.
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James A. Prasoonkumar Abhishek R. Altug Joydeep
Valerio Surti Appu Koker Ray