Haynes and Boone, LLP
Parameterized dummy cell insertion for process enhancement
The present disclosure relates to parameterized dummy cell insertion for process enhancement and methods for fabricating the same. In accordance with one or more embodiments, methods include providing an integrated circuit (IC) design layout with defined pixel-units, simulating thermal effect to the IC design layout including each pixel-unit, generating a thermal effect map of the IC design layout including each pixel-unit, determining a target absorption value for the IC design layout, and performing thermal dummy cell insertion to each pixel-unit of the IC design layout based on the determined target absorption value.
Taiwan Semiconductor Manufacturing Company, Ltd.
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additional additional inventional additional
Ru-Gun Wen-Hao Tsong-Hua Wen-Chun Ying-Chou
Liu Liu Ou Huang Cheng