Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Semiconductor device
 There is herein disclosed a semiconductor device comprising an internal cell area 1 on which various logic circuits are formed, an I/O cell area 3 via which a signal is received/transmitted between a pad for connection to the outside and said internal cell area 1, an external pad area 2a formed outside the I/O cell area 3, and an internal pad area 2b formed between the internal cell area 1 and the I/O cell area 3. Since the internal pad area 2b is disposed not only outside the I/O cell area 3, but also between the I/O cell area 3 and the internal cell area 1, the number of pads for the connection to the outside can be increased more than that of a conventional art, and a large number of pins of a chip can be handled. Moreover, since a pad interval does not have to be narrowed, reliability is improved, and manufacture yield is raised. 
Kabushiki Kaisha Toshiba
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H01L H01L H01L
additional inventional inventional
Toshiaki Yoichiro
Mori Hamura