IP & T Group LLP
Memory controller and memory system including the same
There are provided a memory controller and a memory system including the same. The memory controller includes: a processor for generating a command and an address in response to a request from a host, and generating a bin label and a Log Likelihood Ratio (LLR), based on data received from memory devices; a buffer memory for temporarily storing the data, the bin label, and the LLR; and an error correction circuit for performing error correction decoding on the data, using the LLR.
SK hynix Inc.
G G H G G
G06F G11C H03M G06F G11C
inventional inventional inventional inventional additional
Yong Il
Jung