Dicke, Billig & Czaja, PLLC
Duty cycle corrector
A duty cycle corrector comprising a first circuit and a second circuit. The first circuit is configured to receive a clock signal and an inverted clock signal and to obtain a delay signal that indicates a time difference between transitions of the clock signal and the inverted clock signal. The second circuit is configured to receive the clock signal and the inverted clock signal and the delay signal and to delay the clock signal based on the delay signal to provide an output clock signal having substantially a 50% duty cycle.
Infineon Technologies AG
H
H03K
inventional
Jung Pill Joonho Alessandro
Kim Kim Minzoni