Slater & Matsil, L.L.P.
Methods for double-patterning-compliant standard cell design
A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
Taiwan Semiconductor Manufacturing Company, Ltd.
G H H H H
G06F H01L H01L H01L H01L
inventional additional additional additional inventional
Huang-Yu Yi-Kan Gwan Sin Wen-Ju Fung Song Yuan-Te Li-Chun Lee-Chung
Chen Cheng Chang Yang Lee Hou Tien Lu