Read only memory having multi-bit line bit cell
A memory array includes multiple memory cells, multiple bit lines, multiple word lines, and multiple source lines. Each memory cell includes a corresponding transistor and stores first and second data values. The transistor has corresponding first and second bit lines, and a source line for retrieving the first and second data values. The transistor has a gate terminal connected to a corresponding word line for receiving a word line enable signal, a first diffusion terminal connected to ground, and a second diffusion terminal connected to at least one of the corresponding first bit line, second bit line, and the source line for determining the first and second data values. The second diffusion terminal may be floating for determining the first and second data values.
FREESCALE SEMICONDUCTOR,INC.
G G G H G G
G11C G11C G11C H01L G11C G11C
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Manmohan Paramjeet
Rana Singh