Apparatus for operational analysis of computers
 An apparatus for operational analysis of computing devices which, when coupled to the address, data, and control buses of a computer, displays a representation of a selectable subgroup of the bus signals on a bit map display for each occurrence of a selectable condition. The bits of the least and most significant halves of the selected subgroup define the horizontal and vertical coordinates of a display pixel activated upon occurrence of the selectable condition. Selectable groups are address and data bus signals. An optional condition is specification of bit values of signals on the buses. Selectable control bus signal conditions are read or write and input/output or memory. The display is latched with the state of the selectable subgroup upon occurrence of the selectable conditions thereby remaining stable until the next occurence of the selectable conditions. Efficient adaptability to a variety of computer types is provided for by interchangeable personality interconnection modules that interconnect an optimized set of digital logic gates with the computer control bus signals and control condition selection switches. In a preferred embodiment the display is an array of Light Emitting Diodes which are energized by X and Y decoders in accordance with the group of signals selected to be displayed. 
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James D.
Lewis