Lowe Hauptman Ham & Berner, LLP
Adaptive write bit line and word line adjusting mechanism for memory
A memory includes a capacitor coupled to a write bit line or a word line. An initializer is configured to initialize a voltage level at a first node between the capacitor and the write bit line or a word line. An initial level adjuster is configured to adjust a voltage level of a second node at one terminal of the capacitor. A pulse generator configured to supply a pulse to the initial level adjuster to control the initial level adjuster. A boost signal is configured to be supplied to a third node on the other terminal of the capacitor opposite the first node to boost a voltage level of the write bit line lower than ground or to boost a voltage level of the word line higher than a power supply voltage.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Chung-Cheng Ming-Zhang Hank
Chou Kuo Cheng