Oliff & Berridge, PLC
Semiconductor memory device
The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define connection wirings of a flip-flop. A p+ type well contact region is provided for every two of the memory cells arranged in the Y-axis direction.
Seiko Epson Corporation
Y G H
Y10S G11C H01L
additional inventional inventional
Takafumi Satoru Takashi Masahiro
Noda Kodaira Kumagai Takeuchi