Haynes and Boone, LLP
Enhanced FinFET process overlay mark
An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Kuei-Shun Meng-Wei Chia-Chu Chi-Kang Chi-Wen
Chen Chen Liu Chang Hsieh