Blakely, Sokoloff, Taylor & Zafman LLP
Integrated circuit I/O using a high performance bus interface
 A memory subsystem for storing and retrieving data. At least one memory device Includes a bus Interface. The memory device has at least one memory section comprised of a plurality of memory cells. The bus interface of the at least one memory device couples the memory device to a bus. The bus comprises a group of controlled impedance transmission lines for carrying substantially all information necessary for a single memory device to receive a transaction request, including a memory transaction request, and for carrying substantially all information necessary for a single memory device to respond to the transaction request. The number of signaling lines is substantially less than the number of bits in the information necessary to request a memory transaction to store or retrieve data from the memory cells. Memory device selection information is time-multiplexed on the bus with other memory transaction request information. 
Rambus Inc.
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Michael Mark
Farmwald Horowitz