Conley, Rose & Tayon
Apparatus and method for modifying status bits in a reorder buffer with a large speculative state
 A superscalar microprocessor implements a reorder buffer to support out-of-order execution of instructions. To reduce the time delay for identifying mispredicted instructions, prioritizing mispredicted instructions, canceling instructions subsequent to the mispredicted instruction and reading status information from the reorder buffer, the availability of an instruction tag, which identifies the instruction being executed, during the execution of the instruction is utilized. The reorder buffer receives the tag of the instruction issued to the functional unit. In parallel with the execution of the instruction, the reorder buffer generates hit masks identifying instructions to be canceled in the event of a mispredicted branch. In parallel, status information from the instruction (or instructions) being executed is selected from the reorder buffer and prioritization masks are generated. Therefore, if a mispredicted branch is detected, the instructions that need to be canceled can be readily identified and the instruction status information is readily available. 
Advanced Micro Devices, Inc.
G G
G06F G06F
inventional inventional
Thang M. Teik-Chung
Tran Tan