Jaffery Watson Mendonsa & Hamilton LLP
Handling pipeline submissions across many compute units
One embodiment provides for a general-purpose graphics processing unit multiple processing elements having a single instruction, multiple thread (SIMT) architecture, the multiple processing elements to perform hardware multithreading during execution of multiple warps of threads, wherein a warp is a group of parallel threads; a scheduler to schedule a set of sub-warps to the multiple processing elements at sub-warp granularity, wherein a sub-warp is a sub-group of parallel threads, a warp includes multiple sub-warps, and the scheduler is to schedule threads in a first sub-warp of a first warp of threads to execute concurrently with the threads in a second sub-warp of a second warp of threads; and a logic unit including hardware or firmware logic, the logic unit to group active threads for execution on the multiple processing elements.
Intel Corporation
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inventional additional inventional
Balaji Joydeep Altug
Vembu Ray Koker