Oblon, Spivak, McClelland, Maier & Neustadt
Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through
An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.
Kabushiki Kaisha Toshiba
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Yoshihisa Shigeyoshi Yasuo Masahiko Masaki Ryouhei Fujio Hiroshi Ryozo Kazunori Riichiro Satoshi
Iwata Watanabe Itoh Chiba Momodomi Kirisawa Masuoka Iwahashi Nakayama Ohuchi Shirota Inoue