Sampling clock generation circuit of video signal
 A recording apparatus receives a video signal containing a horizontal sync signal and a data signal comprised of a given number of image bit data arranged within each horizontal scanning period, and stores the number of image bit data in synchronization with the horizontal sync signal. A voltage-controlled oscillator produces in synchronization with the horizontal sync signal a frequency signal having a frequency higher than that of the sync signal. A divider frequency-divides the frequency signal by a given factor to produce a number of sampling pulses corresponding to the given number of image bit data. A data sampling circuit receives the data signal for sampling therefrom the number of image bit data in response to the corresponding sampling pulses to thereby write the image bit data into memory. Another divider frequency-divides the frequency signal by the product of the given factor and the given number to produce a feedback signal. A comparator compares the phase of the feedback and sync signals with each other to produce a control signal effective to maintain the VCO to continuously produce the frequency signal synchronized with the horizontal sync signal. 
Seiko Instruments & Electronics Ltd.
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Kaneo Shinya Fumihiro Yoshio Kenichi
Yamaguchi Watanabe Tanaka Shimada Matsushima