Schwabe, Williamson & Wyatt, P.C.
Integrated circuit die having reduced defect group III-nitride structures and methods associated therewith
Embodiments of the present disclosure are directed toward an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate and a buffer layer disposed over the semiconductor substrate. The buffer layer may have a plurality of openings formed therein. In embodiments, the IC die may further include a plurality of group III-Nitride structures. Individual group III-Nitride structures of the plurality of group III-Nitride structures may include a lower portion disposed in a respective opening of the plurality of openings and an upper portion disposed over the respective opening. In embodiments, the upper portion may include a base extending radially from sidewalls of the respective opening over a surface of the buffer layer to form a perimeter around the respective opening. Other embodiments may be described and/or claimed.
Intel Corporation
H H H H H H H H H H H H H H H H H
H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L
additional inventional additional inventional additional inventional additional additional additional inventional inventional additional additional inventional additional inventional additional
Sansaptak Ravi Seung Hoon Han Wui Robert S. Marko Sanaz K.
Dasgupta Pillarisetty Sung Then Chau Radosavljevic Gardner