Eschweiler & Associates, LLC
Overlay sampling methodology
One embodiment relates to a method to achieve enhanced overlay control while maintaining manufacturing throughput for a fabrication process. Locations of a plurality of alignment structures on a wafer comprising a plurality of reticle fields are determined with a layout tool to define a layout-based wafer map. The topography of the wafer is then measured as a function of wafer position by a surface measuring tool. The layout-based wafer map is then projected onto the measured wafer topography to define a modeled wafer map. A subset of alignment structure locations are measured with an alignment tool in an in-line fabrication flow so as not to delay subsequent fabrication steps. Disagreement between the measured alignment structure locations and modeled alignment structure locations is then minimized mathematically to enhance overlay control while maintaining manufacturing throughput.
Taiwan Semiconductor Manufacturing Co., Ltd.
G G G G H
G06F G16Z G03F G01B H01L
additional additional inventional inventional inventional
Han-Ming Chung-Hao Li-Kong Li-Shiuan
Hsieh Chang Turn Chen