Fish & Richardson P.C.
Bus bandwidth control system
A system includes a central processing unit (CPU), one or more input/output (I/O) ports designed to connect with external devices, a data bus connecting the CPU with the I/O ports, bus request and grant channels, and a bus arbiter that executes a repetitive series of the positive number of cycles, where for each cycle, for each of the bus request and grant channels that is assigned to a bus master and that has a weight equal or greater than a number of cycles already executed, if the bus master assigned to the bus request and grant channel has data waiting to be transferred on the bus then the bus arbiter grants bus access to the bus master to transfer a data packet from the data using the data bus.
Digi International Inc.
G
G06F
inventional
Christopher
Chang