Finnegan, Henderson, Farabow, Garrett & Dunner LLP
Memory system
According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second storages. The first storage includes first memory cells arranged at intersections of the first wiring lines and the second wiring lines. Each of the third wiring lines is connected to any one of the first wiring lines. Each of the fourth wiring lines is pre-associated with a logical address specified by a host apparatus. The second storage includes second memory cells arranged at intersections of the third wiring lines and the fourth wiring lines. A resistance state of each of the second memory cells is set to a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between the logical address and the first wiring line.
Kabushiki Kaisha Toshiba
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Yusuke Yuuichiro Takao Yoshifumi Jiezhi Kazuya
Higashi Mitani Marukame Nishi Chen Matsuzawa