Blakely, Sokoloff, Taylor & Zafman
Method and apparatus for implementing refresh in a synchronous DRAM system
 A synchronous DRAM system with internal refresh is controlled by a refresh signal issued by an oscillator or memory controller coupled to the DRAM. By locating the oscillator on the processor or memory controller better control of the frequency of refresh is achieved, particularly, as the signal can be derived from a crystal which is not sensitive to variations in operating conditions. The oscillator drives a refresh signal on a bus or signal line to the DRAM, such that the refresh address counter is incremented and the row identified by the refresh address counter is refreshed. 
Rambus, Inc.
G
G11C
inventional
James A. Frederick A. Matthew M. John B. Mark A. Michael P.
Gasbarro Ware Griffin Dillon Horowitz Farmwald