Conley, Rose & Tayon, PC
Storage device having varying access times and a superscalar microprocessor employing the same
 A storage device having varying access times is provided. The storage device incorporates a direct-mapped cache and a set-associative cache, which are accessed in parallel. If a hit occurs in the direct-mapped cache, then the data is forwarded in the same clock cycle as the requested address is conveyed to the storage device. If a hit occurs in the set-associative cache, then the data is forwarded in a subsequent clock cycle and the associated cache line is moved into the direct-mapped cache. The cache line stored in the direct-mapped cache in the storage location that is to be used for the cache line being moved is stored into the set-associative cache in the location vacated by the moved line. In this manner, the most recently accessed cache line is stored in the direct-mapped cache and other recently accessed cache lines are stored in the set-associative cache. 
Advanced Micro Devices, Inc.
G G G
G06F G06F G06F
inventional inventional inventional
Thang M.
Tran