Duane Morris LLP
Enhanced refresh circuit and method for reduction of DRAM refresh cycles
A method and circuits are disclosed for refreshing a memory module. After receiving a refresh address identifying a word line to be refreshed, the refresh address is located in one of a predetermined number of memory blocks of the memory module that is monitored. It is further determined whether the word line has been accessed while the memory block is being monitored. If it is determined that the word line has not been accessed, the word line is refreshed. If it is determined that the word line has been accessed, the refreshing operation is skipped for that word line.
Taiwan Semiconductor Manufacturing Co., Ltd.
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G11C G11C G11C
inventional additional inventional
Chung-Cheng
Chou