High speed flash memory
For realizing high speed flash memory, bit line is multi-divided for reducing parasitic capacitance, so that local bit line is quickly discharged when reading a memory cell and multi-stage sense amps are used, wherein the multi-stage sense amps are composed of a first dynamic circuit serving as a local sense amp connecting to the local bit line through a read transistor, a second dynamic circuit serving as a segment sense amp for reading the local sense amp, and a tri-state inverter serving as an amplify circuit of a global sense amp for reading the segment sense amp. When reading data, a cell current difference is converted to a time difference for differentiating low threshold data and high threshold data by the multi-stage sense amps. And a buffered data path is connected to the global sense amp for achieving fast data transfer. Additionally, alternative circuits and memory cell structures are described.
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Juhan
Kim