Patterson + Sheridan, LLP
Method of fabricating air-gap spacer for N7/N5 finFET and beyond
Embodiments disclosed herein relate to an improved transistor with reduced parasitic capacitance. In one embodiment, the transistor device includes a three-dimensional fin structure protruding from a surface of a substrate, the three-dimensional fin structure comprising a top surface and two opposing sidewalls, a first insulating layer formed on the two opposing sidewalls of the three-dimension fin structure, a sacrificial spacer layer conformally formed on the first insulating layer, wherein the sacrificial spacer layer comprises an aluminum oxide based material or a titanium nitride based material, and a second insulating layer conformally formed on the sacrificial spacer layer.
Applied Materials, Inc.
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Tatsuya E. Raymond Hoiman Chih-Yang Nam Sung Bingxi Sun Shiyu
Sato Hung Chang Kim Wood Sun