Beyer Weaver & Thomas LLP
Composite spacer scheme with low overlapped parasitic capacitance
A method and composition for a composite spacer with low overlapped capacitance includes a low-k dielectric spacer layer. A first spacer is deposited on a partially formed semiconductor device having a gate oxide stack, followed by a low dielectric constant spacer layer. Anisotropic etching of the combined layers form spacers surrounding the gate oxide stack.
LSI Logic Corporation
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Chien-Hwa Ming-Yi
Chang Lee