Duane Morris LLP
Triple-pattern lithography layout decomposition
Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.
Taiwan Semiconductor Manufacturing Co., Ltd.
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Wen-Ju Chin-Chang Chien Lin Min-Yuan Hung Lung
Yang Hsu Ho Tsai Lin