Frishauf, Holtz, Goodman & Woodward
Thin film memory cell
 A memory cell has a thin film memory transistor and a thin film selective transistor. The thin film memory transistor has a charge trapping structure and a positive-negative-charge occurrence structure. The charge trapping structure includes a first thin film semiconductor layer, an insulating memory gate layer formed on the first thin film semiconductor layer, and a memory gate electrode. The positive-negative-charge occurrence structure includes an impurity high density layer with a portion facing the memory gate electrode. The thin film selective transistor is coupled to the thin film memory transistor in a serial form and has an only n-channel occurrence structure which includes a second thin film semiconductor layer, an insulating selective gate layer formed on the second thin film semiconductor layer and being thicker than the insulating memory gate layer, and a selective gate electrode formed on said insulating selective gate layer. 
Casio Computer Co., Ltd.
H G H
H01L G11C H01L
inventional inventional inventional
Hiroshi Syunichi Hiroyasu
Matsumoto Sato Yamada