Slater Matsil, LLP
Multi-chip packages with multi-fan-out scheme and methods of manufacturing the same
A package may include a first chip having a first surface and a second surface opposite the first surface; a first redistribution line (RDL) coupled to the first surface of the first chip; a second chip having a first surface and a second surface opposite the first surface, the first surface of the second chip facing the first chip; a second RDL disposed between the first chip and the second chip and coupled to the first surface of the second chip; a conductive via laterally adjacent to the second chip, the conductive via coupled to the second RDL; and a molding compound disposed between the second chip and the conductive via.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Jie Hsien-Wei
Chen Chen