Reducing read data strobe latency in a memory system
A read activity detector circuit for use in a random access memory array includes a plurality of synchronizer circuits operative to receive a plurality of respective reference clock signals having a frequency that is substantially the same as a core reference clock and having different phases relative to one another. Each of the synchronizer circuits, in response to a first control signal presented thereto, generates an output signal having a rising edge or a falling edge which is substantially aligned to a rising edge or a falling edge of the reference clock signal corresponding thereto. The activity detector circuit further includes a controller operative to receive the respective output signals from the plurality of synchronizer circuits and to generate an output signal as a function thereof which is indicative of data to be read from the random access memory array.
Agere Systems Inc.
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Jin Song Jia Jing Tao Wen Michael L.
Liu Wang Wang Zhu Snodgrass