Method for fabricating double implanted LDD transistor self-aligned with gate
 An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment member and a heavily doped junction is aligned with the outboard alignment members. 
Xerox Corporation
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inventional inventional additional
Tiao-Yuan
Huang