Lowe Hauptman Ham & Berner, LLP
Methods for manufacturing array substrates
Disclosed is a patterned photoresist layer on a passivation layer, formed by a lithography process with a multi-tone photomask, having a non-photoresist region, a thin photoresist pattern, and a thick photoresist pattern. The passivation layer corresponding to the non-photoresist region is removed, thereby forming vias to expose a part of a drain electrode in a TFT and a part of a top electrode in a storage capacitor, respectively. The thin photoresist pattern is then ashed to expose the passivation layer in a pixel region. Thereafter, a conductive layer is selectively deposited on the exposed passivation layer and on the sidewalls/bottoms of the vias. Subsequently, the remaining thick photoresist pattern is ashed.
Chimei Innolux Corporation
H
H01L
inventional
Cheng-Hsu
Chou