Conley, Rose & Tayon, PC
Superscalar microprocessor including a decoded instruction cache configured to receive partially decoded instructions
 A decoded instruction cache which stores both directly executable and microcode instructions for concurrent dispatch to a plurality of issue positions. An instruction address required by a superscalar microprocessor is first presented to the decoded instruction cache. If the address is not present in the decoded instruction cache, the instruction bytes are retrieved either from an instruction cache or main memory. In either case, a group of instruction bytes are conveyed to an early decode unit, which performs partial decoding on the instructions therein. These partially decoded instructions are conveyed to the decoded instruction cache for storage. If the first instruction conveyed from the group of instruction bytes is a directly executable instruction, the partially decoded information corresponding to the first instruction is stored in a cache line selected according to the opcode of the first instruction. Directly executable instructions subsequent to the first instruction in the group of instruction bytes may be stored in succeeding locations in the same cache line. If the first instruction is a microcode instruction, operand information provided by the early decode unit is stored to one or more cache lines including directly executable instructions which, when executed, effectuate the operation of that microcode instruction. When a read is performed on a valid line in the decoded instruction cache, partially decoded instructions already aligned for dispatch are conveyed to a plurality of issue positions. 
Advanced Micro Devices, Inc.
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Thang M.
Tran