Fish & Richardson P.C.
Semiconductor device, electronic component, and electronic device
Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating.
Semiconductor Energy Laboratory Co., Ltd.
G G G G G G
G11C G11C G06F G06F G11C G06F
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Tatsuya Takahiko Kiyoshi Wataru
Onuki Ishizu Kato Uesugi