Jaffery Watson Mendonsa & Hamilton LLP
Coordination and increased utilization of graphics processors during inference
A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor. The method may further include analyzing the information to determine one or more portions of hardware relating to the processor capable of supporting the one or more tasks, and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.
Intel Corporation
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Vasanth Elmoustapha Abhishek R. Kamal Chandrasekaran John C. Linda L. Altug Balaji Dukhwan Mike B. Sara S. Joydeep Liwei Sanjeev Prasoonkumar Justin E.
Ranganathan Ould-Ahmed-Vall Appu Sinha Sakthivel Weast Hurd Koker Vembu Kim Macpherson Baghsorkhi Ray Ma Jahagirdar Surti Gottschlich