Schwegman Lundberg & Woessner, P.A.
Partition-aware grid graph based hierarchical global routing
Aspects of the present disclosure address improved systems and methods of partition-aware grid graph based routing for integrated circuit designs. Consistent with some embodiments, a method may include accessing a design layout that defines a layout of components of an integrated circuit design, and includes one or more partitions. The method may further include building a uniform grid graph by superimposing a uniform grid structure over the design layout and inserting additional grid lines into the grid structure such that each partition boundary is aligned with a grid line. The method may further include removing redundant grid lines from the non-uniform grid graph resulting from inserting the additional grid lines, the result of which is the partition-aware grid graph. The method further includes using the partition-aware grid graph to route the integrated circuit design.
Cadence Design Systems, Inc.
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inventional inventional inventional
Mehmet Can Zhuo Gracieli Wen-Hao
Yildiz Li Posser Liu