Fernandez & Associates, LLP
Parallel test circuit and method for wide input/output DRAM
 The present invention discloses a parallel test circuit and method for testing even bit line and odd bit line in a memory block simultaneously. The parallel test circuit comprises an even test circuit for testing an even bit line and an odd test circuit for testing an odd bit line. The parallel test circuit also includes a write circuit for writing data to a bit line, a read circuit including a data sense amp, an output buffer, and a comparator. Furthermore, the present invention provides the capability to conduct disturbance test in neighboring even and odd cells. 
Silicon Access Networks, Inc.
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G11C G11C
inventional inventional
Hing Juhan
Wong Kim