Hamilton, DeSanctis & Cha
Systems and methods for equalizer optimization in a storage access retry
Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails.
LSI Corporation
G G G G G G G
G11B G11B G11B G11B G11B G11B G11B
additional inventional inventional inventional inventional inventional additional
Richard Hongwei Jingfeng Yuan Xing
Rauschmayer Song Liu Lee