Slater Matsil, LLP
Method and apparatus for asynchronous processor with fast and slow mode
A clock-less asynchronous processing circuit or system is configured to operation in a plurality of modes. In an initialization mode (e.g., reset, initialization, boot up), a self-clocked generator associated with the asynchronous circuit is configured to generate an active complete signal (to latch output processed data) within a first period of time after receiving a trigger signal. In a normal mode, the self-clocked generator is configured to generate the active complete signal within a second period of time after receiving the trigger signal. In one embodiment, during the initialization mode, the asynchronous circuit latches the output slower than when in the normal mode.
HUAWEI TECHNOLOGIES CO., LTD.
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Wuxian Wen Tao Qifan Yiqun
Shi Tong Huang Zhang Ge