Integrated circuits adaptable to interchange between clock and data lanes for use in clock forward interface receiver
An integrated circuit includes a first multi-lane interface having a plurality of first lanes, a second multi-lane interface having a plurality of second lanes; a first layer of clock lane selection units arranged to select one or two of the first and second lanes and output signals on the one or two selected lanes; a second layer of clock lane selection units arranged to select the one or two selected lanes as one or two clock lane and output signals on the one or two selected clock lane; and a plurality of sampling units, each coupled to second layer of clock lane selection units, each arranged to sample one of the first and second lanes according to the signal on the selected clock lane.
M31 Technology Corporation
G G
G06F G06F
inventional inventional
Ching-Hsiang Yueh-Chuan Pin-Hao
Chang Lu Feng