Amin, Turocy & Watson, LLP
Transistor with improved self-aligned contact
Systems, methods, and devices facilitating a transistor with an improved self-aligned contact are provided. In one example, a method comprises depositing a dielectric layer onto a first gate region and a second gate region of a semiconductor device, wherein the first gate region and the second gate region are separated by a substrate contact region, and wherein the dielectric layer has a first etch sensitivity to an inter-layer dielectric; and depositing a sacrificial layer onto the dielectric layer, wherein the sacrificial layer has a second etch sensitivity to the inter-layer dielectric that is greater than the first etch sensitivity.
INTERNATIONAL BUSINESS MACHINES CORPORATION
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Juntao Dexin Kangguo Zhenxing
Li Kong Cheng Bi