Split multiplier array and method of operation
A multiplier circuit for use in a data processor. The multiplier circuit contains a partial products generating circuit that receives a multiplicand value and a multiplier value and generates a group of partial products. The multiplier circuit also contains a split array for adding the partial products. A first summation array has a first group of adders that sum the even partial products to produce an even summation value. A second summation array has a second group of adders that sum the odd partial products to produce an odd summation value. The even and odd summation values are then summed to produce the output of the multiplier.
National Semiconductor Corporation
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Daniel W.
Green