Birch, Stewart, Kolasch & Birch, LLP
ESD protection networks with NMOS-bound or PMOS-bound diode structures in a shallow-trench-isolation (STI) CMOS process
Novel PMOS-bound and NMOS-bound diodes for ESD protection, together with their application circuits, are disclosed in this invention. The PMOS-bound (or NMOS bound) diode has a PMOS (or an NMOS) structure. The source/drain region enclosed by the control gate of the PMOS (or NMOS) is used as an anode (or cathode) of the PMOS-bound (or NMOS-bound) diode. The base of the PMOS (or NMOS) is used as a cathode (or anode) of the PMOS-bound (or NMOS-bound) diode. The control gate prevents any shallow trench isolation region from forming beside the p-n junction of the PMOS-bound (or NMOS-bound) diode, such that the ESD sustaining level doesn't suffer from the formation of the STI regions. Furthermore, by ensuring proper bias to the control gate during an ESD event, the turn-on speed of the PMOS-bound or NMOS-bound diode can be increased, such that the overall ESD level of an IC chip is improved. By applying the PMOS-bound or NMOS-bound diode, ESD protection circuits for I/O buffer, power-rail ESD clamping circuits and whole-chip ESD protection systems are also provided.
Taiwan Semiconductor Manufacturing Co., Ltd.
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additional inventional inventional
Wen-Tai Ming-Dou Hun-Hsien
Wang Ker Chang