McDermott Will & Emery LLP
Non-volatile semiconductor memory device and method for reading the same
In a reference cell 202, first and second cells 50 and 52 having the same structure as that of a memory cell are provided. A memory cell current IREF1 of the first cell 50 is set to be a minimum value of a memory cell current after an erase operation. A memory cell current IREF2 of the second cell 52 is set to be a maximum value of a memory cell current after a write operation. The read circuit 206 compares a memory cell current Icell with a current (IREF1+IREF2)/2 and outputs a comparison result. A current source for use in erase verification and write verification may be used in place of the first and second cells 50 and 52. 
Matsushita Electric Industrial Co., Ltd.
G
G11C
inventional
Toshiki
Mori