BPSG, SA-CVD liner/P-HDP gap fill
Device leakage due to spacer undercutting is remedied by depositing a BPSG, SA-CVD oxide liner and flowing it into the undercut regions, followed by gap filling with a P-doped HDP oxide layer. Embodiments include depositing a BPSG, SA-CVD oxide liner containing 4 to 6 wt.% boron, at a thickness of 1,000 &aring; to 1,800 &aring;, over closely spaced apart non-volatile transistors and heating during or subsequent to deposition to flow the BPSG, SA-CVD oxide liner into the undercut regions of the sidewall spacers of the gate stacks. Gap filling is then completed by depositing the layer of P-doped HDP at a thickness of 6,000 &aring; to 10,000 &aring;.
Advanced Micro Devices, Inc.
H H
H01L H01L
inventional inventional
Minh Van Tyagamohan Kelwin King Wai Wenmei Dawn Kuo-Tung
Ngo Gottipati Ko Li Hopper Chang