Kilpatrick Townsend & Stockton LLP
Low core power leakage structure in IO receiver during IO power down
A receiver includes a first transfer gate, a first inverter, a second inverter, a second transfer gate, a third inverter, and a fourth inverter connected in series, a first power supply supplying power to the first and second inverters, a second power supply supplying power to the third and fourth inverters, a third power supply supplying power to the second transfer gate, first and second signals having opposite logic levels for controlling the first transfer gate. The third power supply is significantly lower than the first or second power supply. The leakage current of the receiver is significantly reduced in the core when the second power supply remains on but the first power supply is turned off while the performance of the receiver remains the same.
Semiconductor Manufacturing International (Beijing) Corporation Semiconductor Manufacturing International (Shanghai) Corporation
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Jie Yan Kai
Chen Geng Zhu