Laff, Whitesel, Conte & Saret, Ltd.
Memory controller which can carry out a high speed access when supplied with input addresses with a time interval left between the input addresses having the same row address
 In a memory controller supplied with a first succession of first input addresses having a common row address and supplied with a second succession of second input addresses having the common row address with a time interval left between the first succession of input first addresses and the second succession of input second addresses, a coincidence detector produces a coincidence signal when a trailing row address of the row addresses of the first input addresses coincides with a leading row address of the row addresses of the second input addresses. When supplied with the coincidence signal, a timing controller already causes the multiplexer to deliver a third succession of a leading row address of the row addresses of the first input addresses and column addresses of the first input addresses to a memory device. The timing controller causes the multiplexer in response to the coincidence signal to deliver a fourth succession of column addresses of the second input addresses to the memory device with the time interval left between the third succession of the leading row addresses of the row addresses of the first input addresses and the column addresses of the first input addresses and the fourth succession of the column addresses of the second input addresses. 
NEC Corporation
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G11C G11C G11C G06F
inventional inventional inventional inventional
Kenichi
Yoshida