Marshall, Gerstein & Borun LLP
Internal voltage generating apparatus for a semiconductor memory device
An internal voltage generating apparatus for a semiconductor memory device is described herein. The internal voltage generating apparatus is configured to execute an internal voltage margin test with a small number of pads by installing a forcing pad and fuse (or switch) in an initial reference voltage generating terminal during a multi-chip product test of the DRAM to cut down expenses, and to overcome load or noise due to the forcing pad by cutting (switching off) the fuse after a wafer level test during a normal operation.
Hynix Semiconductor Inc.
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Jun Gi Tae Yun
Choi Kim