Memory device having an internal register
A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.
Rambus Inc.
G G Y G G G G G G
G11C G11C Y02D G11C G11C G11C G11C G06F G11C
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Mark Alan Richard Maurice Craig Edward Frederick Abbot
Horowitz Barth Hampel Ware