Armstrong, Nikaido, Marmelstein & Kubovcik
Plural-bit-per-cell read-only memory
 A plural-bit-per-cell read-only memory constituted by a memory cell array (1), reference cell array (2A, 2B, 2C), and related circuits. In the memory cell array (1), a low resistance ground line (17) crossing the diffusion layer in parallel with the bit lines (15) is arranged for each predetermined length of the diffusion layer, which is used as a common grounding route to the low resistance ground line (17). The reference cell array (2A) includes a plurality of reference cells (211, 212, . . . 21n), and the arrangement of the reference cells (211, 212, . . . 21n) corresponds to the arrangement of the plural-bit memory cells (14) within the predetermined length of the diffusion layer in the memory cells array (1). The transconductance of the reference cells is predetermined in correspondence with the reference voltage values (REF1, REF2, REF3). A column address signal which selects a plural-bit memory cell (14) also selects one of the reference cells (211, 212, . . . 21n) which corresponds to the plural-bit memory cell (14) selected by the column address signal. Thus, in generation of reference voltages (REF1, REF2, REF3), the reference voltage value is corrected taking into consideration the influence of resistance of the diffusion layer according to the location of the plural-bit memory cell (14) selected by the column address signal. 
Fujitsu Limited
G G H G G
G11C G11C H01L G11C G11C
inventional inventional inventional additional inventional
Yasuaki Hiroshi Yasuo
Suzuki Hirao Suzuki