Marger Johnson & McCollom, P.C.
Semiconductor memory device having memory cell arrays capable of accomplishing random access
Disclosed is a nonvolatile semiconductor memory device having a memory cell array by which random access can be performed. The memory cell array structure of the nonvolatile semiconductor memory device having a main memory cell array formed of a plurality of NAND cell strings includes a sub memory cell array having a plurality of NAND cell strings that is provided therein with memory cell transistors. The number of the memory cell transistors in the sub memory cell array is less than that of the memory cell transistors in the NAND cell strings of the main memory cell arrays. The sub memory cell array is operationally connected to main bit lines of the main memory cell array during program and erase operations and is electrically disconnected with the main bit lines during read operation, thereby having a separate read path that is independent from the read path of the main memory cell array.
Samsung Electronics Co., Ltd.
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Seung-Jae Young-Ho
Lee Lim