Memory architecture and system, and interface protocol
A system includes a first integrated circuit. The first integrated circuit includes a direct memory access (DMA) circuit, a first random access memory (RAM) that is accessed by the DMA circuit using DMA, a data/command terminal that communicates with the DMA circuit and that receives a selection signal, and an M-bit data terminal that communicates with the DMA circuit and that receives a write command during a first period when the selection signal has a first state, a write address during a second period when the selection signal has a second state that is different than the first state, and write data during T third periods when the selection signal has the second state. M is an integer greater than one and T is an integer greater than zero. The first period, the second period, and the T third periods are non-overlapping.
Marvell International Ltd.
Y G G G G G G
Y02D G06F G06F G06F G06F G06F G06F
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Saeed Po-Chien
Azimi Chang