McGinn IP Law Group, PLLC
Delayed decision feedback sequence estimator
Disclosed is a delayed decision feedback sequence estimator comprising a delayed decision feedback sequence estimator main unit including DDFSE computing unit group including (L+M) DDFSE computing units, equal in number to a length of each of plurality of blocks into which a received data symbol sequence is divided; wherein (L+M) DDFSE computing units are connected in a pipeline configuration to execute delayed decision feedback sequence estimation of the blocks in parallel; and an edge effect detection and correction circuit that detects an edge effect due to processing the delayed decision feedback sequence estimation of the separated block and corrects a relevant bit error.
The Board of Trustees of the Leland Stanford Junior University Renesas Electronics Corporation
H H
H04L H04L
inventional inventional
Toshitsugu Mark
Kawashima Horowitz