Method of and system for generating a logic configuration for an integrated circuit
A method of placing a circuit design in logic blocks of an integrated circuit is disclosed. The method comprises receiving a circuit design to be implemented in the logic blocks of the integrated circuit; determining clock skew for a clock tree providing clock signals to a plurality of memory elements of the integrated circuit; evaluating timing requirements associated with the circuit design; and transforming the circuit design to a placement configuration, wherein the placement configuration places the circuit design in the logic blocks of the integrated circuit according to the timing requirements of the circuit design and the clock skew for the clock tree.
Xilinx, Inc.
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G06F G06F
inventional additional
Jason H. Qiang
Anderson Wang