Yee & Associates, P.C.
Ternary CAM bitcells
Two new ternary CAM bitcell design options are presented that provide compact layout solutions while maximizing matchline channels routing through the cells. In both layouts, the first inventive layout, an asymmetric layout of the 6T-SRAM bitcell is used to improve ease of layout, density, and performance of ternary CAM cells. In the second inventive layout, n-type diffusions for the SRAM bitcell and the comparison circuit are separated, creating a bitcell having a more even cell aspect ratio.
LSI Logic Corporation
G
G11C
inventional
Ruggero Joseph E. Ramnath
Castagnetti Glenn Venkatraman