Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Nonvolatile semiconductor memory and manufacturing method for the same
A semiconductor memory has a memory cell matrix encompassing (a) device isolation films running along the column-direction, arranged alternately between the memory cell transistors aligned along the row-direction, (b) first conductive layers arranged along the row and column-directions, top surfaces of the first conductive layers lie at a lower level than top surfaces of the device isolation films, (c) an inter-electrode dielectric arranged both on the device isolation films and the first conductive layers so that the inter-electrode dielectric can be shared by the memory cell transistors belonging to different cell columns' relative dielectric constant of the inter-electrode dielectric is higher than relative dielectric constant of the device isolation films, and (d) a second conductive layer running along the row-direction, arranged on the inter-electrode dielectric. Here, upper corners of the device isolation films are chamfered.
Kabushiki Kaisha Toshiba
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H01L H01L Y10T G11C H01L G11C
inventional inventional additional additional inventional additional
Hiroki Atsuhiro Yoshio
Yamashita Sato Ozawa