Gray Cary Ware & Freidenrich LLP
System and method for analyzing error information from a semiconductor fabrication process
A system and method for analyzing error information from a semiconductor fabrication process. The system receives wafer map data describing a plurality of failing chips on a particular semiconductor wafer. The system utilizes the wafer map data to classify each of the failing chips into one of several error categories, such systematic errors, repeated or reticle errors, and random errors. The system further partitions the systematic errors into spatial clusters, which may be compared against a known library of spatial error patterns for identifying the origins of the systematic errors.
Yield Dyamics, Inc.
G H
G01R H01L
inventional inventional
Jonathan B. Weidong
Buckheit Wang