JCIPRNET
Fan-out chip package with dummy pattern and its fabricating method
A fan-out chip package comprises a chip, an encapsulating layer, a first passivation layer, a redistribution wiring layer, a second passivation layer, and a plurality of vertical connectors. The encapsulation encapsulates the sides of the chip. The thickness of the encapsulation is the same as the thickness of the chip. The first passivation layer covers the active surface of the chip and the peripheral surface of the encapsulation. The redistribution layer is formed on the first passivation layer to extend the electrical connection of the chip to the peripheral surface of the encapsulation. The second passivation layer is formed on the first passivation layer. The vertical connectors are embedded in the encapsulation and the redistribution layer. The vertical connectors are only penetrate through the encapsulation protect the redistribution layer from damages.
Powertech Technology Inc.
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inventional inventional additional additional inventional additional inventional inventional additional additional inventional inventional inventional additional inventional additional additional additional additional additional additional additional additional inventional
Chia-Wei Kuo-Ting
Chang Lin