Hogan & Hartson LLP
Semiconductor device with SRAM section including a plurality of memory cells
A semiconductor device having an SRAM section in which a p-well, a first n-well, and a second n-well are formed in a semiconductor substrate. Two n-type access transistors and two n-type driver transistors are formed in the p-well. Two p-type load transistors are formed in the first n-well. The second n-well is located under the p-well and the first n-well and also is connected to the first n-well. The potential of the first n-well is supplied from the second n-well. According to the present invention, the SRAM section can be reduced in size.
Seiko Epson Corporation
Y H H Y
Y10S H01L H01L Y10S
additional inventional additional additional
Takashi Masahiro Satoru Takafumi
Kumagai Takeuchi Kodaira Noda