Wenderoth, Lind & Ponack
Semiconductor memory having a bit position decoder and date re-ordering circuitry for arranging bits in a word of data
 A semiconductor memory device for simultaneously accessing data in groups of four bits includes a memory cell block for storing a plurality of 4- bit words. The memory cell block has a plurality of memory cell outputs which are connected to column gate transistors. A gate control circuit is provided for controlling the column gate transistors to access four consecutive bits of data in the memory cells. The accessed four consecutive bits, including a portion of one word and a portion of a subsequent word, are aligned such that the portion of the subsequent word is followed by the portion of one word. A data re-ordering circuit is provided for re-ordering the accessed consecutive bits to align them such that the portion of one word is followed by the portion of the subsequent word. 
Matsushita Electric Industrial Co., Ltd.
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inventional inventional additional
Toshiki
Mori