Saile Ackerman LLC
MRAM write pulses to dissipate intermediate state domains
A write method for a STT-RAM MTJ is disclosed that substantially reduces the bit error rate caused by intermediate domain states generated during write pulses. The method includes a plurality of “n” write periods or pulses and “n−1” domain dissipation periods where a domain dissipation period separates successive write periods. During each pulse, a write current is applied in a first direction across the MTJ and during each domain dissipation period, a second current with a magnitude equal to or less than the read current is applied in an opposite direction across the MTJ. Alternatively, no current is applied during one or more domain dissipation periods. Each domain dissipation period has a duration of 1 to 10 ns that is equal to or greater than the precession period of free layer magnetization in the absence of spin torque transfer current.
Headway Technologies, Inc.
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Po-Kang Guenole Yuan-Jen
Wang Jan Lee