Blakely, Sokoloff, Taylor & Zafman LLP
Semiconductor memory device capable of easily performing delay locking operation under high frequency system clock
A semiconductor memory device includes a first clock buffer for outputting a first internal clock signal in response to an inverted signal of the system clock signal and for correcting a duty cycle ratio of the first internal clock signal in response to a control signal; a second clock buffer for outputting a second internal clock signal in response to the system clock signal and for correcting a duty cycle ratio of the second internal clock signal in response to the control signal; an analog duty cycle correction circuit for outputting the control signal corresponding to the duty cycle ratio of the first and second internal clock signals; a mixing circuit for mixing the first and second internal clock signals and for outputting a third internal clock signal whose duty cycle is corrected; and a DLL circuit for outputting a delay-locked clock signal by using the third internal clock signal.
Hynix Semiconductor Inc.
G G G H H
G11C G06F G11C H03L H03K
inventional inventional inventional inventional inventional
Seong-Jun Min-Young
Lee You