Muncy, Geissler, Olds & Lowe, P.C.
Detecting circuit, DRAM, and method for determining a refresh frequency for a delay-locked loop module
The present disclosure provides a detecting circuit. The detecting circuit includes a clock module, a clock receiver, a delay-locked loop module, a clock tree module, an off-chip driver, a pad, a phase detector, a voltage-detecting module and a control module. The clock module provides a clock signal to the clock receiver. The clock receiver sends the clock signal to the pad through the delay-locked loop module, the clock tree module and the off-chip driver. The control module is coupled to the voltage-detecting module and the delay-locked loop module. The voltage-detecting module is coupled between the control module and the clock tree module, and is configured to detect a voltage of the clock tree module and to send a voltage comparison information to the control module. The control module is configured to control a refresh frequency of the delay-locked loop module.
NANYA TECHNOLOGY CORPORATION
G G G H G H G G
G11C G11C G11C H03L G11C H03L G11C G11C
inventional inventional inventional inventional inventional inventional inventional inventional
Wen-Ming Chuan-Jen
Lee Chang