Eschweiler & Potashnik, LLC
RRAM cell structure with laterally offset BEVA/TEVA
The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode via and a bottom electrode over a top of the bottom electrode via. A data storage layer is over the bottom electrode and a top electrode is over the data storage layer. A top electrode via is on an upper surface of the top electrode and is centered along a first line that is laterally offset from a second line centered upon a bottommost surface of the bottom electrode via. The first line is perpendicular to the upper surface of the top electrode and parallel to the second line.
Taiwan Semiconductor Manufacturing Co., Ltd.
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Wen-Ting Chin-Chieh Yu-Wen Chih-Yang Hsia-Wei Wen-Chun Kuo-Chi Sheng-Hung
Chu Yang Liao Chang Chen You Tu Shih