Yee & Associates
Method and architecture for detecting random and systematic transistor degradation for transistor reliability evaluation in high-density memory
A self-aligning memory cell design is provided to allow testing of transistors in every cell of a memory circuit. A test array of these cells is fabricated with contact pads in each cell for specific components in the cell. Then, metal lines are provided to couple the contact pads in the test array. The whole test array is then probed via these metal lines. Tests may then be performed to detect random and systematic transistor degradation electrically for all cells in the circuit. Different components in the memory design may be tested by providing contact pads for the components of interest and providing metal lines coupling the contact pads.
LSI Logic Corporation
G H G H H
G11C H01L G11C H01L H01L
inventional inventional additional inventional inventional
Franklin L. Subramanian Ruggero
Duan Ramesh Castagnetti