Harness, Dickey & Pierce, P.L.C.
Semiconductor device having resistance based memory array and method of operation associated therewith
In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array.
Samsung Electronics Co., Ltd.
G G G G G G G G
G11C G11C G11C G11C G11C G11C G11C G11C
inventional inventional inventional inventional additional inventional inventional additional
Kwangjin Taek-Sung Yong-Jun Wooyeong Kwangho Qi Hye-Jin Hyunho
Lee Kim Lee Cho Kim Wang Kim Choi