McClure, Qualey & Rodack, LLP
Power-saving mechanism for memory sub-system in pipelined processor
A pipelined processor for carrying out pipeline processing of instructions, which undergo a plurality of stages, is provided. The pipelined processor includes: a memory-activation indicator and a memory controller. The memory-activation indicator stores content information that indicates whether to activate a first volatile memory and/or a second volatile memory while performing a current instruction. The memory controller is arranged for controlling activation of the first volatile memory and/or the second volatile memory in a specific stage of the plurality of stages of the current instruction according to the content information stored in the memory-activation indicator.
MEDIATEK INC.
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Chang-Chia Yu-Shu Hsing-Chuang
Lee Chen Liu