F. Chau & Assoc., LLC
NAND flash memory device capable of improving read speed
A NAND flash memory device which includes a first page buffer circuit reading main data bits from the main field during a read operation, a second page buffer circuit reading redundant data bits from the redundancy field during the read operation, a first column gate circuit configured to select a part of the read main data bits and a part of the read redundant data bits in response to first column selection signals at the same time, and a second column gate circuit configured to select a part of the selected main data bits in response to second column selection signals.
Samsung Electronics Co., Ltd.
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G11C G11C
inventional inventional
Jung-Hoon Seung-Jae
Park Lee