Michael J. Chang, LLC
Techniques for forming vertical tunneling FETS
Techniques for increasing a source-to-channel tunneling area in TFETs are provided. In one aspect, a method of forming a vertical TFET includes: patterning at least one pair of fins in an undoped semiconductor layer (vertical fin channels) and doped drain layer, filling gaps between the pair of fins with a dielectric; forming gates along outer sides of the pair of fins; partially recessing the dielectric to form a trench in between the pair of fins; forming a doped source layer in the trench overlapping the vertical fin channels. A vertical TFET device formed by the method is also provided, as is a vertical TFET device and method for formation thereof where a positioning of the doped source layer and the gates is reversed.
International Business Machines Corporation
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Peng Kangguo Xin Juntao
Xu Cheng Miao Li