Fish & Richardson P.C.
Normally-off, power-gated memory circuit with two data retention stages for reducing overhead power
The first circuit has a function of retaining data in a first period during which a power supply voltage is supplied. The second circuit has functions of saving the data retained in the first circuit in the first period and retaining the data saved from the first circuit in a second period during which application of the power supply voltage is stopped. The third circuit has functions of saving the data retained in the second circuit in the second period and retaining the data saved from the second circuit in a third period during which application of the power supply voltage is stopped. The second circuit is capable of being written with the data for a shorter time than the third circuit. The third circuit is capable of maintaining the data for a longer time than the second circuit.
Semiconductor Energy Laboratory Co., Ltd.
G G G
G11C G11C G11C
inventional additional inventional
Yasuyuki Kiyoshi Takuro
Takahashi Kato Ohmaru