Park, Vaughan, Fleming & Dowler LLP
Batch process for three-dimensional integration
A chip package is described which includes a first chip having a first surface and first sides having a first side-wall angle, and a second chip having a second surface and second sides having a second side-wall angle, which faces and is mechanically coupled to the first chip. The chip package is fabricated using a batch process, and the chips in the chip package were singulated from their respective wafers after the chip package is assembled. This is accomplished by etching the first and second side-wall angles and thinning the wafer thicknesses prior to assembling the chip package. For example, the first and/or the second side walls can be fabricated using wet etching or dry etching. Therefore, the first and/or the second side-wall angles may be other than vertical or approximately vertical.
ORACLE INTERNATIONAL CORPORATION
H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H
H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L
additional additional additional additional additional additional inventional additional additional additional additional inventional additional additional additional additional additional additional additional inventional additional inventional additional additional additional inventional additional additional additional additional additional additional additional additional additional additional
Ashok V. John E. Hiren D.
Krishnamoorthy Cunningham Thacker