DRAM including pseudo negative word line
For increasing retention time in DRAM, pseudo negative word line scheme is realized such that voltage of a local bit line pair is always higher than that of an unselected word line for applying negative gate voltage, but selected word line is asserted to a pre-determined voltage. For implementing the scheme, swing voltage of the local bit line pair is limited by a write path connecting to a global bit line pair when writing, and the local bit line pair is also limited when reading, because selected local bit line is slightly changed with charge re-distribution and unselected local bit line is at floating state. For minimizing sensing current, a locking signal is generated to cut off a current path from the global bit line pair to a local sense amp. And various alternative circuits are described for implementing the pseudo negative word line scheme.
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G11C G11C
inventional inventional
Juhan
Kim