William Park & Associates Ltd.
Semiconductor memory apparatus and test method thereof
A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.
SK Hynix Inc.
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inventional inventional inventional inventional
Tae Sik Hyung Dong Jun Gi Sang Hoon Sang Jin
Yun Lee Choi Shin Byeon