Edwards Wildman Palmer LLP
Coreless package substrate and fabrication method thereof
A coreless package substrate is provided, including: a circuit buildup structure including at least a dielectric layer, at least a circuit layer and conductive elements; first electrical contact pads embedded in the lowermost dielectric layer of the circuit buildup structure; a plurality of metal bumps formed on the uppermost circuit layer of the circuit buildup structure; a dielectric passivation layer disposed on a top surface of the circuit buildup structure and the metal bumps; and second electrical contact pads embedded in the dielectric passivation layer and electrically connected to the metal bumps. With the second electrical contact pads being engaged with the metal bumps and having top surfaces thereof completely exposed, the bonding strength between the second electrical contact pads and a chip to be mounted thereon and between the second electrical contact pads and the metal bumps can be enhanced.
Unimicron Technology Corporation
H H H H H Y H H H H H Y H
H01L H01L H01L H01L H05K Y10T H01L H01L H01L H01L H01L Y10T H01L
inventional additional additional additional inventional additional additional additional additional inventional additional additional additional
Chung-W. Tzyy-Jang
Ho Tseng