Low voltage serial to parallel to serial charge coupled device
 This serial to parallel to serial (SPS) charge coupled device (CCD) shift register memory has a serial output shift register with stage gate electrode structures that are interdigitated with the gate electrode structures of each last stage of a plurality of parallel shift registers to transfer interlaced data bits from the parallel shift registers to the serial output register in a sequential order. This is done without employing a fixed voltage midway between the highest clock voltage and reference potential in the parallel registers in what is commonly called a midway store to regulate the transfer of data to the interdigitated gate electrode structures. 
International Business Machines Corp.
G H
G11C H01L
inventional inventional
Jean M. John J. Yelandur R.
Ferre Byrne Gopalakrishna