Nicholson De Vos Webster & Elliott LLP
Apparatus and method for managing data bias in a graphics processing architecture
An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, one embodiment of an apparatus comprises: a processor comprising one or more cores to execute instructions and process data, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory coupled to the GPU, the GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication, for each of a plurality of blocks of data, whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, then the data is to be accessed by the GPU from the GPU memory without necessarily accessing the processor's cache coherence controllers and wherein requests for the data from the processor cores are processed as uncached requests, preventing the data from being cached in the one or more cache levels of the processor.
Intel Corporation
G G G G G G G G G G G
G06F G06F G06F G06F G06T G06F G06F G06F G06F G06T G06F
additional additional inventional inventional inventional inventional additional inventional inventional inventional additional
Joydeep Abhishek R. Altug Balaji
Ray Appu Koker Vembu