Morgan, Lewis & Bockius LLP
Memory system with calibrated data communication
A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.
Rambus Inc.
H G H G G G G G G G G G G G G G
H04L G06F H04L G06F G06F G06F G06F G06F G06F G06F G06F G06F G11C G06F G06F G06F
inventional inventional additional additional inventional inventional inventional inventional inventional inventional additional inventional inventional inventional inventional inventional
Bruno W. Kevin S. Donald C. Jared LeVan Tsyr-Chyang Roxanne Leung Stefanos Mark A. Jun Benedict Chung-Kwong
Garlepp Donnelly Stark Zerbe Ho Vu Yu Sidiropoulos Horowitz Kim Lau