Tutunjian & Bitetto, P.C.
Approach to minimization of strain loss in strained fin field effect transistors
A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure.
International Business Machines Corporation
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Zhenxing Kangguo Peng Juntao
Bi Cheng Xu Li