Adaptive instruction prefetching and fetching memory system apparatus and method for microprocessor system
A method and system of prefetching and fetching processor instructions is designed for reduced code fraction, for scaled packed instructions before runtime, and for adaptive, concurrent instruction prefetch and fetch at runtime. The invention is designed for reducing energy consumption of the instruction cache memories by accurately accessing the instructions that will be executed and by terminating instruction prefetch after prefetching instructions from the possible paths. The invention is also designed for improving performance by reducing branch instructions and by prefetching and fetching instructions adaptively. In particular, compiled native instructions are converted to mixed packed nonnative and non-packed native instructions for generating more streamlined code and storing the native instructions of the packed instructions in dedicated, separate regions of distinct addresses in the concurrent accessible instruction cache and main memories. The packed instructions are dynamically reverted to native instructions to be prefetched and fetched concurrently.
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inventional inventional
Yong-Kyu
Jung