McClure, Qualey & Rodack, LLP
Method for determining sampling phase of sampling clock signal and associated electronic device
An electronic device includes a clock generating circuit, a receiving circuit and a training circuit. The clock generating circuit generates a sampling clock signal, a phase-early sampling clock signal and a phase-late sampling clock signal. The receiving circuit samples received data according to the sampling clock signal, the phase-early sampling clock signal and the phase-late sampling clock signal to generate a sample result. The training circuit controls the clock generating circuit to generate the sampling clock signal and the corresponding phase-early sampling clock signal and phase-late sampling clock signal that have different phases in a plurality of different time intervals, respectively, to cause the receiving circuit to generate a plurality of sample results. The training circuit further determines a sampling phase of the sampling clock signal according to the sample results.
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Jyun Yang Chih-Hung Wei-Yung Chun-Chia Ming-Han
Shih Lin Wang Chen Weng