Programmable logic block of FPGA using phase-change memory device
Provided is a programmable logic block of a field-programmable gate array (FPGA). The programmable logic block includes a pull-up access transistor connected to a power source, an up-phase-change memory device connected to the pull-up access transistor, a down-phase-change memory device connected to the up-phase-change memory device, an output terminal between the up-phase-change memory device and the down-phase-change memory device, and a pull-down access transistor connected to the down-phase-change memory device and a ground. The resistance values of the up-phase-change memory device and the down-phase-change memory device are individually programmed.
Electronics and Telecommunications Research Institute
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inventional inventional inventional
Sung Min Young Sam Byoung Gon Yong-Joo Seung-Yun Soonwon
Yoon Park Yu Kim Lee Jung