NSIP Law
Synapse array, pulse shaper circuit and neuromorphic system
A synapse array based on a static random access memory (SRAM), a pulse shaper circuit, and a neuromorphic system are provided. The synapse array includes a plurality of synapse circuits. At least one synapse circuit among the plurality of synapse circuits includes at least one bias transistor and at least two cut-off transistors, and the at least one synapse circuit is configured to charge a membrane node of a neuron circuit connected with the at least one synapse circuit using a sub-threshold leakage current that passed through the at least one bias transistor.
Samsung Electronics Co., Ltd. Postech Academy-Industry Foundation
G G G
G11C G06N G06N
inventional inventional inventional
Jun Seok Hyun Surk Jae Yoon Hwasuk
Kim Ryu Sim Cho