Conley, Rose & Tayon, PC
Method and apparatus for predecoding variable byte length instructions for fast scanning of instructions
 A superscalar microprocessor is provided that includes a predecode unit configured to predecode variable byte-length instructions prior to their storage within an instruction cache. The predecode unit is configured to generate a plurality of predecode bits for each instruction byte. The plurality of predecode bits, called a predecode tag, associated with each instruction byte include a number of bits that indicates a number of byte positions to shift each instruction byte in order to align the instruction byte with a decode unit. Each decode unit includes a fixed number of instruction byte positions for storing bytes of instructions. A start byte of an instruction is conveyed to a first instruction byte position. The predecode tags are used by a multiplex and shift unit of an instruction alignment unit to shift the instruction bytes such that the start byte of an instruction is stored in a first instruction byte position of a decode unit. The subsequent instruction bytes of an instruction are stored in the remaining instruction bytes of the decode unit. Accordingly, relatively fast multiplexing of instructions may be obtained. The instruction alignment unit is not required to scan the instruction bytes for start bytes and end bytes. The predecode tag for each instruction byte indicates a number of byte positions to shift that byte. Accordingly, the instruction alignment unit mnay be a simple multiplexing and shift unit. 
Advanced Micro Devices, Inc.
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inventional inventional inventional
Thang M.
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