Antonelli, Terry, Stout & Kraus
Nonvolatile semiconductor memory having enhanced speed for erasing and programming
 An arrangement is provided to enhance the speed in the operation of erasing and programming of a nonvolatile semiconductor memory that is driven by a single supply voltage and to reduce the number of transistors making up the subword decoder circuit thereby minimizing the size of the device. For this purpose, in the subword decoder circuits WDi1-WDij that drive the word lines Wi1-Wij, the block selection address lines Bip and Bin generated from the first address line group are used as supply voltages for the inverter circuit that controls the voltage of the word line, and the gate selection address line Gj generated from the second address line group is used a gate input line. 
Hitachi, Ltd.
G G G
G11C G11C G11C
inventional inventional inventional
Yoshinobu Hitoshi Masataka Keiichi Toshihiro Katsutaka
Nakagome Kume Kato Yoshida Tanaka Kimura