Harness, Dickey & Pierce, PLC
Methods of fabricating fan-out wafer level packages and packages formed by the methods
A fan-out wafer level package may include at least two semiconductor chips; an insulating layer covering portions of a first semiconductor chip; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and/or an external terminal on the insulating layer. The first semiconductor chip may be stacked relative to the second semiconductor chip. The redistribution line pattern may be electrically connected to the at least two semiconductor chips. The external terminal may be electrically connected to the redistribution line pattern. A fan-out wafer level package may include at least three semiconductor chips; an insulating layer covering portions of first semiconductor chips; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and/or an external terminal on the insulating layer. The first semiconductor chips may be stacked relative to the second semiconductor chip.
SAMSUNG ELECTRONICS CO., LTD.
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Jin-Woo Hogeon Seokhyun
Park Song Lee