Heslin, Rothenberg Farley & Mesiti P.C.
Shrink process aware assist features
Methods for fabricating integrated circuits are provided. In one example, a method includes providing a circuit structure layer over a substrate and at least one etch layer over the circuit structure layer, in the at least one etch layer patterning at least one primary pattern feature having at least one primary pattern feature dimension and at least one assist pattern feature having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension, reducing the at least one primary pattern feature dimension and closing the assist pattern feature to form an etch pattern, and etching a circuit structure feature using the etch pattern.
GLOBALFOUNDRIES INC.
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Azat Wenhui Lei Tamer Ryan Ryoung-Han
Latypov Wang Sun Coskun, Jr. Kim