Antonelli, Terry, Stout & Kraus
Data output buffer for a semiconductor memory
 A data output buffer is provided in connection with a semiconductor memory, such as a pseudostatic RAM, which is capable of high speed operation with respect to memory data readout. The buffer includes a latch circuit comprising a pair of NAND gate circuits having input and output terminals connected in cross connection, a pair of precharge MOSFETs provided respectively between the noninverted and inverted input terminals of the latch circuit, a pair of CMOS NAND gates which transfer the inverted signal of the latch circuit according to an inverted timing signal and a pair of series-connected MOSFETs effecting a pull-up/pull-down arrangement which receives the inverted signal of the output signal of the NAND gates. 
Hitachi, Ltd. Hitachi VLSI Engineering Corp.
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Michitaro Yutaka Katsuyuki Takeshi Nobuo Masahiro Shouji Kanehide Kiichi
Kanamitsu Shimbo Sato Kajimoto Kato Ogata Kubono Kenmizaki Manita