Method and apparatus for parallel processing of semiconductor chip designs
In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.
International Business Machines Corporation
G
G06F
inventional
Michael W. Dazhuang J. Ruchir Louise H. Anthony
Dotson Ma Puri Trevillyan DeGroff Drumm