JCIPRNET
Resistive random access memory having charge trapping layer, manufacturing method thereof, and operation thereof
A resistive random access memory (RRAM) including a first electrode, a second electrode, and a charge trapping layer is provided. The second electrode is located on the first electrode. The charge trapping layer is located between the first electrode and the second electrode. The charge trapping includes a first region and a second region. The first region has a first dopant and is close to the first electrode. The second region has a second dopant and is close to the second electrode.
Winbond Electronics Corp.
H H H H G G H H G H H
H01L H01L H01L H01L G11C G11C H01L H01L G11C H01L H01L
inventional inventional inventional inventional additional inventional inventional inventional inventional inventional inventional
Boris Tuo-Hung Che-Chia
Hudec Hou Chang