Trellis IP Law Group, PC
Selection of initial states for formal verification
A computer is programmed to automatically select a state or a set of states of a digital circuit that are visited during simulation, for use as one or more initial states by a formal verification tool. Such automatic selection of one or more simulation states reduces the set of all simulation states to a small subset, thereby to address the state space explosion problem. Depending on the embodiment, the programmed computer uses one or more criteria provided by a library and/or by the user, in making its selection of states. Such criteria may be based on a property (assertion/checker) of the digital circuit and/or a signal generated during simulation. Furthermore, after such criteria (also called “primary criteria”) are applied, the selected states may be pruned by application of additional criteria (also called “secondary criteria”) prior to formal analysis.
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inventional inventional
Chian-Min Richard Ramesh Christophe G. Ping Fai Jeremy R. James Andrew Garrard Kalyana C.
Ho Sathianathan Gauthron Yeung Levitt Seawright Mulam