Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions
A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the first semiconductor material can be grown over the lattice-mismatched semiconductor layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.
International Business Machines Corporation
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Huajie Haining S. An L. Oleg G. Dureseti
Chen Yang Steegen Gluschenkov Chidambarrao