System for improving endurance and data retention in memory devices
A memory system includes a memory block having at least one memory cell. The current is sensed after the erase operations of the memory cell. A signal is generated in response to the current dropping below a predetermined level after the erase operations of the memory cell. The stress on the memory cell is reduced to a first reduced level for erase operations occurring subsequent to the current dropping below the predetermined level.
Chartered Semiconductor Manufacturing Ltd.
G G
G11C G11C
inventional inventional
Wenbo Maggie L. F. Siow Lee Fei
Li Tan Chwa Xu