McClure, Qualey & Rodack, LLP
Method for layout generation with constrained hypergraph partitioning
A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
G G G G G
G06F G06F G06F G06F G06F
inventional additional inventional additional inventional
Jui-Feng Hung-Wen Abhishek Wei-Yi Hung-Ming Tsun-Yu Hsien-Hsin Sean Po-Cheng
Kuan Huang Patyal Hu Chen Yang Lee Pan