Tutunjian & Bitetto, P.C.
Integrated strained stacked nanosheet FET
Transistors include stress liners, with one or more semiconductor structures between the stress liners. The stress liners provide a stress on the one or more semiconductor structures. A gate is formed over and around the one or more semiconductor structures. A source and drain region is formed on the one or more semiconductor structures on opposite sides of the gate, between the stress liners.
INTERNATIONAL BUSINESS MACHINES CORPORATION
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Xin Ramachandra Juntao Kangguo
Miao Divakaruni Li Cheng