Duane Morris LLP
Apparatus and method for measuring degradation of CMOS VLSI elements
The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages.
Taiwan Semiconductor Manufacturing Co., Ltd.
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G01R G01R
inventional inventional
Yung-Fu Fang-Shi Jordan Chin-Hao Manoj M. Chih-Cheng Cheng Yen Hsu-Feng
Lin Lai Chang Mhala Lu Weng Hsueh