IP & T Group LLP
Memory device with different parity regions
The present disclosure memory includes a controller for a semiconductor memory device, the device including a memory cell array including a plurality of pages. The controller includes a memory control module suitable for translating a logical address for data provided from a host to a physical address representing one of the plurality of pages, and determining one of a plurality of operation modes based on the physical address and pre-stored parity-related information. The controller further includes and an error correction code circuit suitable for generating parity-data for the data provided from the host according to the determined operation mode.
SK Hynix Inc.
G G G
G06F G11C G11C
inventional additional inventional
Yun Bong Suk Kwang Gil Bok Sung Hoon Min Sang
Lee Park Choi Cho Park