Process method of source drain spacer engineering to improve transistor capacitance
A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are thereby facilitated. Compensation regions are formed within a substrate by implanting dopants relatively deeply over source and drain regions formed within the substrate. The compensation regions are spaced apart slightly less than are the source and drain regions. This spacing affects potential contours and reduces junction capacitances within the transistor. The different distances between the source and drain regions and the compensation regions are achieved by forming and selectively adjusting sidewall spacers adjacent to a gate structure of the transistor. These spacers serve as guides for the dopants implanted into the substrate to form the source and drain regions and the compensation regions.
Texas Instruments Incorporated
H H H H H H H
H01L H01L H01L H01L H01L H01L H01L
inventional inventional inventional inventional inventional inventional inventional
Zhiqiang Jihong Kaiping
Wu Chen Liu