Jaffery Watson Mendonsa & Hamilton LLP
Sector cache for compression
In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.
Intel Corporation
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Lakshminarayanan Joydeep Atlug Balaji Prasoonkumar Kiran C. Pattabhiraman David Abhishek R. Vasanth
Striramassarma Ray Koker Vembu Surti Veernapu K Puffer Appu Ranganathan