Fish & Richardson P.C.
Semiconductor device
A plurality of memory cells included in a memory cell array are divided into a plurality of blocks every plural rows. A common bit line is electrically connected to the divided bit lines through selection transistors in the blocks. One of the memory cells includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first channel formation region. The second transistor includes a second channel formation region. The first channel formation region includes a semiconductor material different from the semiconductor material of the second channel formation region.
Semiconductor Energy Laboratory Co., Ltd.
H G H G
H01L G11C H01L G11C
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Takanori Hiroki Kiyoshi Shuhei
Matsuzaki Inoue Kato Nagatsuka