Leydig, Voit & Mayer, Ltd.
Method and apparatus for de-jittering a clock signal
The present invention discloses a de-jittering method for a clock signal, which is implemented by adopting a controllable frequency divider and includes: taking the clock signal to be de-jittered as a reference signal, and comparing a feedback clock signal outputted by the controllable frequency divider with the reference signal; generating the control signal that is then transmitted to the controllable frequency divider; the controllable frequency divider performs frequency division upon the input high-frequency signal to generate a stable clock, and the stable clock is outputted as the feedback clock signal which has been de-jittered. The present invention also discloses a de-jittering apparatus for implementing the above-mentioned method, which includes: a circuit for generating a control signal and a controllable frequency divider. By applying the present invention, the de-jittering circuit for clock signal can be simple. What's more, transition between T1 clock frequency and E1 clock frequency can also be implemented to meet practical requirements better.
Huawei Technologies Co., Ltd.
H H
H04J H03L
additional inventional
Jun
Xia