Techniques for generating bit reliability information in a post-processor using an error correction constraint
Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.
Hitachi Global Storage Technologies Netherlands, B.V.
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Ivana Mario Richard Leo Ksenija Yuan Xing Travis Roger Zongwang Bruce Alexander
Djurdjevic Blaum Galbraith Lakovic Lee Oenning Li Wilson