Pennie & Edmonds LLP
Method of manufacturing a junction in a semiconductor device
 The present invention relates to a method of manufacturing a junction in a semiconductor device. When forming an elevated source/drain junction (ESD) of a buried channel field effect transistor (BC-FET) using a selective epitaxial growth (SEG) technique, a self-aligned epitaxial silicon (SESS) is formed on the lower portion of a gate side-wall spacer, resulting in the improvement of a short channel characteristic by suppressing a facet occurred when forming an elevated source/drain junction (EDS) of the buried channel field effect transistors (BC-FETs) using a selective epitaxial growth (SEG) technique as well as the increase of the current density by lowering the series resistance of source/drain extension. 
Hyundai Electronics Industries Co., Ltd.
H
H01L
inventional
Noh Yeal Seung Chul In Seok Sahng Kyoo Jung Ho
Kwak Lee Yeo Lee Lee