Trop, Pruner & Hu, P.C.
Shared cache memories for multi-core processors
Embodiments of shared cache memories for multi-core processors are presented. In one embodiment, a cache memory comprises a group of sampling cache sets and a controller to determine a number of misses that occur in the group of sampling cache sets. The controller is operable to determine a victim cache line for a cache set based at least in part on the number of misses.
Intel Corporation
G G
G06F G06F
inventional inventional
Yen-Kuang Wenlong Yu Christopher J. Changkyu
Chen Li Chen Hughes Kim