J.C. Patents
Method of fabricating complementary metal-oxide-semiconductor transistor and metal-oxide-semiconductor transistor
A method of fabricating a metal-oxide-semiconductor transistor is provided. A first gate structure and a second gate structure are formed on a substrate. The first gate structure has a dimension greater than the second gate structure. Then, first lightly doped drain regions are formed in the substrate on two sides of the first gate structure. A lightly doped drain annealing process is performed. Next, second lightly doped drain regions are formed in the substrate on two sides of the second gate structure. First spacers are formed on the sidewalls of the first gate structure and second spacers are formed on the sidewalls of the second gate structure at the same time. Afterwards, first source/drain regions are formed in the substrate on two sides of the first spacers and second source/drain regions are formed in the substrate on two sides of the second spacers. A source/drain annealing process is performed.
United Microelectronics Corp.
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Kun-Hsien Li-Shian Shyh-Fann Tzyy-Ming Wen-Han Jing-Yi Chia-Wen Cheng-Tung
Lee Jeng Ting Cheng Hung Huang Liang Huang