Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
Jitter reduction in clock and data recovery circuits
Techniques are disclosed relating to clock and data recovery circuitry. In some embodiments, a slicing circuit may be configured to sample an input signal to generate a first and second sampled data signal. In some embodiments, a phase detector circuit may be configured to compare the phases of the first and second sampled data signals. In some embodiments, a first charge pump may be configured to supply a first current to a circuit node, and a second charge pump may be configured to supply a second current to the circuit node. In some embodiments, a voltage-controlled oscillator may be configured to adjust a frequency of first and second clock signals based on a voltage of the circuit node.
Apple Inc.
H H H H H H H H
H04L H04L H04L H03L H03L H03L H03L H03L
inventional inventional inventional inventional inventional inventional inventional inventional
Wenbo Ming-Shuan Sanjeev K.
Liu Chen Maheshwari