Volentine & Whitt, PLLC
Semiconductor device having additive latency
A semiconductor device receives a command corresponding to a memory access operation and performs the memory access operation after an additive latency period. The additive latency period begins when the command is received. The semiconductor device comprises a phase controller for controlling a phase of a clock signal and outputting a phase-controlled clock signal, and a controller for generating and outputting a control signal for enabling the phase controller that is disabled, at a predetermined time in the additive latency period.
Samsung Electronics Co., Ltd.
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additional inventional inventional
Jung-hwan Yang-ki
Choi Kim