Blakely, Sokoloff, Taylor & Zafman LLP
Apparatus and method for caching lock conditions in a multi-processor system
 In a computer system, an apparatus for handling lock conditions wherein a first instruction executed by a first processor processes data that is common to a second processor while the second processor is locked from simultaneously executing a second instruction that also processes this same data. A lock bit is set when the first processor begins execution of the first instruction. Thereupon, the second processor is prevented from executing its instruction until the first processor has completed its processing of the shared data. Hence, the second processor queues its request in a buffer. The lock bit is cleared after the first processor has completed execution of its instruction. The first processor then checks the buffer for any outstanding requests. In response to the second processor's queued request, the first processor transmits a signal to the second processor indicating that the data is now not locked. 
Intel Corporation
G
G06F
inventional
Wen-Hann Gurbir Mandar S. Matthew A. Nitin V. Konrad K.
Wang Singh Joshi Fisch Sarangdhar Lai