J.C. Patents
Low power dynamic logic circuit
A low power dynamic logic circuit. By shifting a discharge NMOS transistor of a conventional dynamic logic circuit between an output terminal and a logic block, plus an additional charge and discharge control, the operation speed and power consumption of a dynamic circuit can be effectively improved. Using the charge redistribution to speed up the circuit operation and to reduce the body effect that affects the operation speed, the speed of the novel dynamic logic circuit is enhanced. By transferring the lump capacitor of the charge/discharge, the dynamic power can be effectively reduced. The lower power dynamic logic circuit can be used independently or combined with a conventionally dynamic logic circuit.
National Chung Cheng University
H
H03K
inventional
Ching-Rong Jinn-Shyan Ching-Wei
Chang Wang Yeh