Panitch Schwarze Belisario & Nadel LLP
Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller
A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.
eASIC Corporation
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H01L G06F H03K
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Chee-Wei Ivan Ranko L. Seow-Sung Chong-Teik Alexander Alexander Mikhail Igor
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