Eschweiler & Potashnik, LLC
Methodology for pattern density optimization
The present disclosure relates to a method of data preparation. The method, in some embodiments, performs a first data preparation process using a data preparation element. The first data preparation process modifies a plurality of shapes of an integrated chip (IC) design that comprises a graphical representation of a layout used to fabricate an integrated chip. A plurality of additional shapes are added to the IC design using an additional shape insertion element. The plurality of additional shapes are separated from the plurality of shapes by one or more non-zero distances. A second data preparation process is performed using the data preparation element, after performing the first data preparation process. The second data preparation process modifies the plurality of additional shapes.
Taiwan Semiconductor Manufacturing Co., Ltd.
G G
G03F G06F
inventional inventional
Cheng-Hsuan Chun-Hung Hung-Chun Wen-Chun Cheng-Kun Ru-Gun Ping-Chieh Ming-Hui Wen-Hao
Huang Wu Wang Huang Tsai Liu Wu Chih Liu