Oliff & Berridge, PLC
Method of manufacturing layered chip package
A layered chip package includes a main body, and wiring disposed on at least one side surface of the main body. The main body has: a main part having a top surface and a bottom surface and including a plurality of layer portions stacked; and a plurality of terminals arranged on at least one of the top and bottom surfaces of the main part and electrically connected to the wiring. A manufacturing method for the layered chip package includes: fabricating a plurality of first layered substructures each including a plurality of pre-separation main bodies arrayed; fabricating a second layered substructure by stacking the first layered substructures; cutting the second layered substructure into a block in which a plurality of pre-separation main bodies are arrayed in two directions; forming the wiring simultaneously for the plurality of pre-separation main bodies included in the block; and separating the pre-separation main bodies from each other.
Headway Technologies, Inc. SAE Magnetics (H.K.) Ltd.
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Atsushi Hiroyuki Yoshitaka Hiroshi
Iijima Ito Sasaki Ikejima