J.C. Patents
Chip package structure and fabricating method thereof
A chip package structure including a chip, a lead frame, first bonding wires and second bonding wires is provided. The chip has an active surface, first bonding pads and second bonding pads, wherein the first bonding pads and the second bonding pads are disposed on the active surface. The chip is fixed below the lead frame, and the lead frame includes inner leads and bus bars. The inner leads and the bus bars are disposed above the active surface of the chip, and the bus bars are located between the inner leads and the corresponding first bonding pads. The first bonding wires respectively connect the first bonding pads and the bus bars. The second bonding wires respectively connect the bus bars and a part of the inner leads. The third bonding wires respectively connect the second bonding pads and the other of the inner leads.
ChipMOS Technologies (Bermuda) Ltd. ChipMOS Technologies, Inc.
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additional additional additional additional additional inventional additional additional additional additional additional additional additional inventional additional additional additional additional additional additional additional additional inventional
Yu-Ren Ya-Chi Chun-Ying I-Hsin
Chen Chen Lin Mao