Haynes and Boone, LLP
Logic compatible RRAM structure and process
A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
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Hsia-Wei Kuo-Chi Yu-Wen Wen-Ting Chin-Chieh Chih-Yang
Chen Tu Liao Chu Yang Chang