Patterson + Sheridan, LLP
Test circuits for testing a die stack
Device(s) and method(s) related generally to a wafer or die stack are disclosed. In one such device, a die stack of two or more integrated circuit dies has associated therewith test circuits corresponding to each level of the die stack each with a set of pads. A test data-input path includes being from: a test data-in pad through a test circuit to a test data-out pad of each of the test circuits; and the test data-out pad to the test data-in pad between consecutive levels of the test circuits. Each of the set of pads includes the test data-in pad and the test data-out pad respectively thereof. A test data-output path is coupled to the test data-out pad of a level of the levels.
XILINX, INC.
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Albert Shih-Huai Cheang-Whang Myongseob Amitava Henley Nui
Lin Chang Kim Majumdar Liu Chong