Cache control for concurrent access
 The disclosure enables concurrent access to a cache by main storage and a processor by means of a cache control which provides two cache access timing cycles during each processor storage request cycle. The cache is accessible to the processor during one of the cache timing cycles and is accessible to main storage during the other cache timing cycle. No alternately accessible modules, buffering, delay, or interruption is provided for main storage line transfers to the cache. 
International Business Machines Corporation
G
G06F
inventional
Carleton E. Spurgeon G. Edward C.
Werve Hogan Wong