Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Dynamic random access memory device with the combined open/folded bit-line pair arrangement
 A semiconductor memory device of the present invention comprises a plurality of word lines formed on a substrate, a plurality of bit lines perpendicular to the word lines and divided into bit-line groups in the column direction along the word line, each group containing three bit lines, and arrays of memory cells arranged at the intersections of word lines and bit lines, wherein two memory cells are placed at two of every three adjacent intersections arranged in each of the row and column directions, and where these memory cell arrays are divided into subarrays in the row direction, each of the cell arrays is divided into cell blocks in the row direction, two of the three bit lines in each bit-line group along the bit line are crossed each other between adjacent cell blocks, and a plurality of sense amplifiers are placed between adjacent cell arrays so as to correspond to cell blocks. 
Kabushiki Kaisha Toshiba
G H G
G11C H01L G11C
inventional inventional inventional
Shigeyoshi Daisaburo
Watanabe Takashima