Volentine & Whitt, PLLC
Method of forming interconnection lines for semiconductor device
The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern is formed on the via filling material. The via filling material and the interlayer insulating layer are anisotropically etched using the photoresist pattern as an etch mask to form a trench. A residual portion of the via filling material is removed using two wet etch processes. After removing the residual portion of the via filling material, a conductive layer pattern is formed in the via hole and the trench.
Samsung Electronics Co., Ltd.
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inventional inventional additional inventional inventional
Hong-Jae Ki-Kwan Seung-Jin Kyoung-Woo Young-Jin Jae-Hak
Shin Park Lee Lee Wee Kim