Oblon, Spivak, McClelland, Maier & Neustadt
Dynamic semiconductor memory device having high integration density
 A bipolar transistor Q.sub.1 having a collector formed of a substrate region SUB of a MOS transistor M.sub.1, a base formed of the drain region of the MOS transistor and an emitter formed on the base and connected to a bit line BL is connected between the bit line BL and a memory cell MC formed of the MOS transistor M.sub.1 and and a capacitor C.sub.1 and the current amplifying operation of a bipolar transistor is used for data readout. 
Kabushiki Kaisha Toshiba
H G G G H
H01L G11C G11C G11C H01L
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Kazumasa Fumio Akihiro Shigeyoshi Takehiro Katsuhiko Tsuneaki
Sunouchi Horiguchi Nitayama Watanabe Hasegawa Hieda Fuse