Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
Logic simulator and logic simulation method
According to one embodiment, a logical circuit to be simulated includes a timing network and a specific logical device. The timing network transmits a logical value change of an input signal in correspondence with an elapse of time or clock number increments. The specific logical device receives a timing network output signal that appears at an exit node of the timing network, and a logical value change or a logical value after change of the clock. When predetermined constraint information represents a constraint that a time period or the demanded number of clock cycles needed for a transition of a signal level change to pass through a signal path in the timing network is equal to or smaller than a predetermined numerical value (or equal to or larger than a predetermined numerical value), it is checked if the signal input to the specific logical device violates the predetermined constraint information.
Kabushiki Kaisha Toshiba
G
G06F
inventional
Kenji
Yoshida