Oliff & Berridge, PLC
Layered chip package and method of manufacturing the same
A layered chip package includes a main body and wiring. The main body includes a main part including a plurality of stacked layer portions, and a plurality of terminals disposed on the top and bottom surfaces of the main part. The wiring includes a plurality of lines electrically connected to the plurality of terminals. The plurality of lines include a plurality of common lines and a plurality of layer-dependent lines. Each of the plurality of layer portions includes a plurality of common electrodes electrically connected to the plurality of common lines, and a selective connection electrode selectively electrically connected to only the layer-dependent line that the layer portion uses among the plurality of layer-dependent lines. The selective connection electrode varies in shape depending on which of the layer-dependent lines it is electrically connected to.
Headway Technologies, Inc. SAE Magnetics (H.K.) Ltd.
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Hiroyuki Yoshitaka Hiroshi Atsushi
Ito Sasaki Ikejima Iijima