Harness, Dickey & Pierce, P.L.C.
Methods of manufacturing devices including a buried gate cell and a bit line structure including a thermal oxide buffer pattern
A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.
Samsung Electronics Co., Ltd.
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Joon-Yong Young-Ju Jung-Hyun Augustin Jinwoo Hyo-Dong Yoon-Chul Je-Min Hyeon-Kyu Sang-Jun
Choe Lee Kim Hong Ban Cho Park Lee Lee