Multicore communication processing
Mechanisms for processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.
International Business Machines Corporation
H
H04L
inventional
Natarajan Herman D. Colin B. Christoph Jan-Bernd Jean L. Fabrice J. Philippe Claude Chih-jen
Vaidhyanathan Dierks, Jr. Verrilli Raisch Themann Calvignac Verplanken Damon Basso Chang