IP & T Group LLP
Memory controller and operating method thereof
The present disclosure relates to an electronic device. A memory controller having improved read interleaving and write interleaving performance may include a buffer memory temporarily storing data chunks read from a sacrificial area, a target die information manager generating target die information on a plurality of memory dies in which the data chunks are respectively stored according to logical address counts of the data chunks corresponding to the plurality of memory dies, respectively, determined based on correspondence information between the plurality of memory dies and logical addresses provided from a host, and a write operation controller controlling the plurality of memory dies so that the data chunks temporarily stored in the buffer memory are stored in the plurality of memory dies on the basis of the target die information.
SK hynix Inc.
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Seok Jun
Lee