Steinberg & Whitt
Synchronous memory device having an internal register
 The present invention is directed to an integrated circuit device having at least one memory section including a plurality of memory cells. The device includes an internal register to store an identification value which identifies the device on a bus. The device further includes interface circuitry, coupled to the bus, to receive identification information and a read request. The interface circuitry includes a plurality of output drivers and comparison circuitry. The output drivers are coupled to the bus to output data on the bus in response to the read request. The data is output synchronously with respect to first and second external clock signals when the comparison circuitry determines the identification information corresponds to the identification value. 
Rambus Inc.
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Michael Mark
Farmwald Horowitz