Volentine & Whitt, PLLC
Semiconductor memory device having power saving mode
A semiconductor memory device includes a memory cell array arranged in rows and columns, a row decoder and a control circuit. The row decoder drives word lines connected to the memory cell array by decoding a received row address and being synchronized with an internal clock signal. The control circuit receives a clock signal, a chip select signal and a mode signal, and generates the internal clock signal. The control circuit generates the internal clock signal so that the row decoder does not operate for a predetermined time in response to the chip select signal when the mode signal transitions from a power saving mode to a normal mode.
Samsung Electronics Co., Ltd.
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inventional inventional additional
Hyunsu JaeSeung
Choi Choi