Method for optimizing an integrated circuit layout design
A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.
UNITED MICROELECTRONICS CORP.
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G03F G06F G06F
inventional inventional additional
Ming-Jui Yan-Chun Jing-Yi Ping-I Shih-Ming Te-Hsien
Chen Chen Lee Hsieh Kuo Hsieh