J.C. Patents
Memory structure
A memory structure including a substrate, at least one stacked gate structure, a first spacer conductive layer, and a first contact is provided. The stacked gate structure is located on the substrate and includes a control gate. The control gate extends in a first direction. The first spacer conductive layer is located on one sidewall of the control gate and is electrically insulated from the control gate. The first spacer conductive layer includes a first merged spacer portion and a first non-merged spacer portion. A line width of the first merged spacer portion is greater than a line width of the first non-merged spacer portion. The first contact is connected to the first merged spacer portion. The memory structure can have a larger process window of contact.
United Microelectronics Corp.
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inventional inventional inventional inventional
Chia-Ching Yung-Lin Wang Chun-Sung Shen-De Wei-Chang
Hsu Tseng Xiang Huang Wang Liu