Eschweiler & Potashnik, LLC
Horizontal memory array structure with scavenger layer
Various embodiments of the present disclosure are directed towards a resistive random access memory (RRAM) device including a scavenger layer. A bit line overlying a semiconductor substrate. A data storage layer around outer sidewalls and a top surface of the bit line. A word line overlying the data storage layer. A scavenger layer between the word line and the bit line such that a bottom surface of the scavenger layer is aligned with a bottom surface of the bit line. A lateral thickness of the scavenger layer is less than a vertical thickness of the scavenger layer.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Hung-Li Yu-Sheng Tzu-Chiang Chao-Ching
Chiang Chen Chen Cheng