F. Chau & Associates, LLP
Bit line sensing control circuit for a semiconductor memory device and layout of the same
A layout of a bit line sensing control circuit for a semiconductor memory device includes two bit line pairs extending in a first direction. A power contact is arranged between the two bit line pairs. A power gate is arranged around the power contact. A plurality of sense transistors respectively have a plurality of sense transistor gates. The plurality of sense transistor gates are arranged around the power gate. A pair of control line contacts is arranged in a second direction at an adjacent location outside the two bit line pairs. A control line extends in the second direction and is connected to the power gate through the pair of control line contacts. A power line extends in the second direction adjacent to the control line and is connected to an active area surrounded by the power gate through the power contact.
Samsung Electronics Co., Ltd.
G G G
G11C G11C G11C
inventional inventional inventional
Jae-Hoon Sang-Suk Yun-Sang Jong-Eon
Joo Kang Lee Lee