Oblon, Fisher, Spivak, McClelland and Maier
N scale counter
 An n scale counter includes a shift register having X number of unit delay circuits connected in series and each consisting of a plurality of insulated gate field effect transistors. The unit delay circuits of the shift register are simultaneously supplied with pulses to be counted and each of the delay cicuits is set or reset to an initial state. There is also provided a closed loop circuit including a first gate circuit connected to receive an output signal from the last stage delay circuit as one input terminal, and a logic circuit connected to receive output signals from the first gate circuit and, for example, the first stage delay circuit and produce to the input terminal of the first stage delay circuit an output signal indicating coincidence or incoincidence of its input signals. The counter is capable of counting pulses of (2.sup.x -1) at maximum. A second gate circuit is provided to apply its output signal to the other input terminal of the first gate circuit and output signals of a predetermined combination from the unit delay circuits are supplied to the second gate circuit so that the counter can function as a counter with a counting capacity smaller than that of (2.sup.x -1). 
Tokyo Shibaura Electric Co., Ltd.
H
H03K
inventional
Yasoji Teruaki Tomohisa Kenshi
Suzuki Tanaka Shigematsu Manabe