Muncy, Geissler, Olds & Lowe, P.C.
Sampling circuit
A sampling circuit includes a first latch, a second latch and a signal transition detector. The first latch is disposed on an upstream side of a logic circuit. The second latch is disposed on a downstream side of the logic circuit. The first latch and the second latch respectively switch to opposite states of an opaque state or a transparent state according to trigger signals generated by a reference clock and a control clock. The signal transition detector is configured for detecting whether the signal outputted by the logic circuit is in error or not and outputting a corresponding control clock. The above-mentioned sampling circuit can delay switching the second latch to the opaque state and switching the first latch to the transparent state to correct sampling when a timing error occurs.
NATIONAL CHIAO TUNG UNIVERSITY
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inventional inventional inventional
Shyh-Jye Wei-Chang Chi-Wei Ching-Da Chia-Hsiang
Jou Liu Lo Chan Yang