Memory built in self test circuit and method for generating a hardware circuit comprising the routing boxes thereof
A circuit and a method for performing a memory built in self test (MBIST) are provided. The circuit comprises a plurality of routing boxes and a test controller. The test controller provides test input signals to a plurality of embedded memory blocks, receives data output signals output by the memory blocks in response to the test input signals, and verifies the data output signal based on the test input signals. The routing boxes are placed to form a common bus between the test controller and the memory blocks to transmit the signals between the test controller and the memory blocks.
Faraday Technology Corp.
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inventional inventional additional additional
Che-Chiang Jian-Dai
Chang Pan