Tutunjian & Bitetto, P.C.
Reduction of top source/drain external resistance and parasitic capacitance in vertical transistors
A method of forming a semiconductor device that includes forming at least two semiconductor fin structures having sidewalls with {100} crystalline planes that is present atop a supporting substrate; and epitaxially growing a source/drain region in a lateral direction from the sidewalls of each fin structure. The second source/drain regions have substantially planar sidewalls. A metal wrap around electrode is formed on an upper surface and the substantially planar sidewalls of the source/drain regions. Air gaps are formed between the source/drain regions of the at least two semiconductor fin structures.
INTERNATIONAL BUSINESS MACHINES CORPORATION
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Choonghyun Shogo Kangguo Juntao
Lee Mochizuki Cheng Li