Jaffery Watson Mendonsa & Hamilton LLP
Thread scheduling over compute blocks for power optimization
One embodiment provides for a general-purpose graphics processing unit comprising a processing array including multiple compute blocks, each compute block including multiple processing clusters and a thread dispatch unit to dispatch threads of a workload to the multiple compute blocks based on a parallelism metric, wherein the thread dispatch unit, based on the parallelism metric, is to perform one of a first operation and a second operation, the first operation to distribute threads across the multiple compute blocks and the second operation is to concentrate threads within one of the multiple compute blocks.
Intel Corporation
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G06T G06F G06F Y02D
inventional inventional inventional additional
Balaji Abhishek R. James A. Joydeep Altug
Vembu Appu Valerio Ray Koker