Jones Day
Systems and methods for generating a controllable-width pulse signal
Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.
Taiwan Semiconductor Manufacturing Company Limited
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G04F H03K H03K H03K G04F H03K
inventional inventional additional inventional inventional inventional
Ming Hsien Tsung-Hsien Ruey-Bin Chih-Hsien
Tsai Tsai Sheen Chang