Slater & Matsil, L.L.P
Chip-level ECO shrink
In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed.
Taiwan Semiconductor Manufacturing Company, Ltd.
H G
H01L G06F
additional inventional
Ho Che Chung-Hsing Hsiao-Shu Lee-Chung Huang-Yu Yi-Kan
Yu Wang Chao Lu Chen Cheng