Eschweiler & Associates, LLC
RRAM device with data storage layer having increased height
The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.
Taiwan Semiconductor Manufacturing Co., Ltd.
H H H H H H H
H01L H01L H01L H01L H01L H01L H01L
inventional inventional additional inventional inventional inventional inventional
Manish Kumar Sheng-Hung Chin-Chieh Wen-Ting Kuo-Chi Yu-Wen Chih-Yang Jen-Sheng
Singh Shih Yang Chu Tu Liao Chang Yang