Volentine & Whitt, PLLC
Semiconductor memory devices for alternately selecting bit lines
A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).
Samsung Electronics Co., Ltd.
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Yun-Sang Hyung-Rok Sang-Beom Chul-Woo Dong-Hyun Chan-Kyung Dong-Seok
Lee Oh Kang Park Sohn Kim Kang