Beyer & Weaver
Metal-encapsulated polysilicon gate and interconnect
 Provided are methods of forming a metal layer on the horizontal and vertical surfaces of a polysilicon gate electrode/interconnect in a MOS transistor, and devices having metal-encapsulated gates and interconnects. The metal encapsulation method of the present invention may also provide a layer of metal on the exposed surfaces of the source and drain regions of the transistor. The methods and apparatuses of the present invention allow reductions in device resistance and signal propagation delays. 
LSI Logic Corporation
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Subramanian Ruggero Gary K. Yauh-Ching
Ramesh Castagnetti Giust Liu