Jaffery Watson Mendonsa & Hamilton LLP
Extend GPU/CPU coherency to multi-GPU cores
In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.
INTEL CORPORATION
G G G Y G G G G G G G G
G06F G06N G06N Y02D G06N G06N G06F G06F G06N G06N G06N G06T
inventional inventional inventional additional inventional inventional inventional additional inventional inventional inventional inventional
Abhishek R. Ben J. John C. Narayan Prasoonkumar Kamal Chandrasekaran Rajkishore Eriko Altug Joydeep Justin E. Balaji Sara S. Nicolas C. Feng Tsung-Han
Appu Ashbaugh Weast Srinivasa Surti Sinha Sakthivel Barik Nurvitadhi Koker Ray Gottschlich Vembu Baghsorkhi Galoppo Von Borries Chen Lin