Marger Johnson & McCollom, P.C.
Wafer burn-in test circuit for a semiconductor memory device
 A semiconductor memory device has independently controllable word lines, thereby allowing various background data patterns to be freely written to the memory cells to perform various wafer burn-in tests. This allows the leakage between adjacent memory cells to be efficiently tested by independently controllable word line activation signals, as well as the reliability of bit lines. A wafer burn-in test circuit for performing this improved burn-in test improves the reliability of the device by performing a level transition on the signals that drive the sub word line drivers, thereby eliminating the need to apply a high voltage to one transistor in the sub word line driver. 
Samsung Electronics, Cp. Ltd.
G
G11C
inventional
Yun-Sang
Lee