Sawyer Law Group LLP
Design and use of a spacer cell to support reconfigurable memories
The present invention provides a method and apparatus for reconfiguring a memory array. Aspects of the present invention include fabricating the memory array as at least one row of single-port cells up to a first metal layer. A split word line having first and second word lines is coupled to the single-port cells in each row, wherein the first word line is patterned in the first metal layer, and the second word line is patterned in a second metal layer. The split word line is further coupled to a spacer cell in the row. The method and apparatus further include programming the memory array into custom configurations based on whether the first and second word lines are connected over the spacer cell, or whether the first and second word lines are left unconnected.
LSI Logic Corporation
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Y10S G11C H01L G11C
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Ramnath Rugger Subramanian
Venkatraman Castagnetti Ramesh