Flehr, Hohbach, Test, Albritton & Herbert
Semiconductor memory device with bit line pairs crossed at least once with respect to each other
 A semiconductor memory device of the type with a plurality of bit line pairs and signal lines disposed parallel to these bit line pairs is characterized in that two bit lines forming a pair are crossed at least once in the middle to prevent capacitance imbalance caused by misalignment of the associated signal line. 
Sharp Kabushiki Kaisha
G
G11C
inventional
Masaru Tomoyuki Hirofumi
Nawaki Tagami Higashino