Jaffery Watson Mendonsa & Hamilton LLP
Instructions and logic to perform floating-point and integer operations for machine learning
One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.
Intel Corporation
G G G G G G G G G G G G G G G G G
G09G G06N G06F G06F G06N G06F G06F G06F G06F G06N G06F G06N G06T G06F G06F G06N G06F
inventional additional additional inventional inventional inventional additional inventional inventional inventional additional inventional additional additional inventional inventional inventional
Nicolas C. Kamal Mark A. Tsung-Han Xiaoming Balaji Anbang Rajkishore Ping T. Altug Himanshu Eriko Michael S. Sanjeev Tatiana Vasanth Sanu K. Abhishek R. Joydeep
Galoppo Von Borries Sinha Anders Lin Chen Vembu Yao Barik Tang Koker Kaul Nurvitadhi Strickland Jahagirdar Shpeisman Ranganathan Mathew Appu Ray