Oblon, Fisher, Spivak, McClelland & Maier
Semiconductor memory device
 A dynamic random access memory including a sense amplifier having MOSFETs, which constitute a flip-flop, and an activating MOSFET. A memory cell includes a switching MOSFET and a capacitor having a grooved structure. A dummy cell includes a switching MOSFET and capacitor having a planar structure. The activating MOSFET has its gate coupled to a gate bias generator, which comprises a reference capacitor group consisting of planar type capacitors having a nearly constant capacitance, irrespective of the influence of process parameters, and a monitoring capacitor group consisting of capacitors having the same grooved structure and the same capacitance as the memory cell capacitor. The reference capacitor group, and the monitoring capacitor group are pre-charged. When the sensing operation starts, the reference capacitor group and the monitoring capacitor group are short-circuited, so that a charge reallocation is executed between these groups. When a word line driver functions, the gate of the switching MOSFET of the memory cell is open, thus transferring data of the memory cell capacitor and dummy cell capacitor onto bit line BL and BL. The voltage of the node between the reference and monitoring capacitor groups, which are short-circuited, is applied to the gate of the activating MOSFET of the sense amplifier after a predetermined time delay. 
Kabushiki Kaisha Toshiba
G G
G11C G11C
inventional inventional
Shigeyoshi
Watanabe