McDermott, Will & Emery
Frequency-dividing circuit capable of generating frequency-divided signal having duty ratio of 50%
 A signal obtained through logical operation of an output signal from a K.multidot.T delay circuit delaying a supplied signal by K cycles of an input signal and a feedback signal of an M.multidot.T delay circuit delaying a supplied signal by M cycles of the input signal through a feedback part is supplied to the M.multidot.T delay circuit. Among signals generated by the M.multidot.T delay circuit, signals out of phase by K/2 cycles of the input signal is Ored or ANDed by a duty control circuit for controlling a duty ratio. Alternatively, cascaded latch circuits operating in synchronization with a clock signal have a final output coupled to a first stage input through an inverter. The final output provides a frequency-divided signal. The number of components is reduced, layout efficiency is improved and a frequency-divided signal having a duty ratio of 50% is provided. 
Mitsubishi Denki Kabushiki Kaisha
H
H03K
inventional
Tetsuya
Watanabe