Muir Patent Consulting, PLLC
Wafer-level stack package and method of fabricating the same
A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.
Samsung Electronics Co., Ltd.
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additional additional additional additional additional inventional additional additional additional additional additional additional inventional inventional additional additional additional additional additional additional additional additional additional inventional additional additional additional additional additional additional additional additional additional additional inventional inventional
Hyun-Soo Son-Kwan Ju-Il Ho-Jin In-Young
Chung Hwang Choi Lee Lee