Wenderoth, Lind & Ponack
Column selection circuit of semiconductor memory with transfer gate
 A column selection circuit of a semiconductor memory includes a plurality of transfer gates each of which is arranged between each sense amplifier and each column select gate for gating each column to an internal bus according to a difference between a potential of each bit line and a precharge potential of each data bus. 
Matsushita Electric Industrial Co., Ltd.
G G
G11C G11C
inventional inventional
Akifumi Toshiki
Kawahara Mori