Tung & Associates
Split gate field effect transistor (FET) device employing dielectric barrier layer and method for fabrication thereof
Within both a method for fabricating a split gate field effect transistor and the split gate field effect transistor fabricated employing the method, there is employed a patterned silicon nitride barrier dielectric layer formed covering a first portion of a floating gate and a first portion of a semiconductor substrate adjacent the first portion of the floating gate. Within the first portion of the semiconductor substrate there is eventually formed a source/drain region, and more particularly a source region, when fabricating the split gate field effect transistor. The patterned silicon nitride barrier dielectric layer inhibits when fabricating the split gate field effect transistor ion implant damage of the floating gate and oxidative loss of a floating gate electrode edge.
Taiwan Semiconductor Manufacturing Co., Ltd
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inventional inventional inventional inventional
Chia-Ta Sheng-Wei Jake Wen-Ting Chuan-Li Di-Son
Hsieh Tsaur Yeh Chu Chang Kuo