Ropes & Gray LLP
Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits
Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
Altera Corporation
H
H03M
inventional
Arch Thungoc Tim Tri Chong Toan Thanh Sergey Yuryevich Ramanand
Zaliznyak Tran Hoang Lee Nguyen Shumarayev Venkata