F. Chau & Associates, LLC
Delay locked loop circuit and semiconductor memory device including the same
A delay locked loop circuit includes: a delay locked loop block receiving an external clock and generating a delay locked internal clock; a duty cycle correcting block connected to the delay locked loop block and correcting the duty cycle of the internal clock; and an error detecting unit comparing the voltages of first and second pumping output nodes of the duty cycle correcting block to detect an operation error of the duty cycle correcting block.
Samsung Electronics Co., Ltd.
H
H03L
inventional
Jung-Hwan
Choi