Finch & Maloney PLLC
Techniques for monolithic co-integration of silicon and III-N semiconductor transistors
Techniques are disclosed for monolithic co-integration of silicon (Si)-based transistor devices and III-N semiconductor-based transistor devices over a commonly shared semiconductor substrate. In accordance with some embodiments, the disclosed techniques may be used to provide a silicon-on-insulator (SOI) or other semiconductor-on-insulator structure including: (1) a Si (111) surface available for formation of III-N-based n-channel devices; and (2) a Si (100) surface available for formation of Si-based p-channel devices, n-channel devices, or both. Further processing may be performed, in accordance with some embodiments, to provide n-channel and p-channel devices over the Si (111) and Si (100) surfaces, as desired. In accordance with some embodiments, the disclosed techniques may be used to provide co-integrated III-N-based n-type metal-oxide-semiconductor (NMOS) devices and Si-based p-type metal-oxide-semiconductor (PMOS), NMOS, or complementary MOS (CMOS) devices with different step heights or with a given degree of co-planarity, as desired for a given target application or end-use.
INTEL Corporation
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Marko Han Wui Peter G. Sansaptak
Radosavljevic Then Tolchinsky Dasgupta