Jaffery Watson Mendonsa & Hamilton LLP
Shared local memory tiling mechanism
An apparatus to facilitate memory tiling is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads via access to the memory and tiling logic to apply a tiling pattern to memory addresses for data stored in the memory.
INTEL CORPORATION
G G G G G G G H G G G G G G G H
G06F G09G G06F G06F G06T G06T G06F H04N G06F G06F G06F G06T G06F G09G G06F H04N
additional inventional inventional inventional inventional inventional inventional inventional additional inventional inventional inventional additional additional additional inventional
Joydeep Subramaniam M. Altug Prasoonkumar Abhishek R.
Ray Maiyuran Koker Surti Appu