Static random access memory timing tracking circuit
An apparatus and method for executing a write operation in a static random access memory (SRAM) array including memory cells that are coupled to a plurality of word lines and to a plurality of bit lines are provided. A clock signal is generated to start a write operation. A pulse is generated on the plurality of word lines in response to the clock signal. An operation voltage of the SRAM array is lowered for a period of time during the write operation. The period of time is controlled and the pulse is ended using a tracking circuit. The tracking circuit includes a plurality of tracking memory cells. The plurality of tracking memory cells have a timing characteristic that emulates a timing characteristic of the SRAM array during the write operation. The tracking circuit controls the period of time and ends the pulse based on the emulated timing characteristic.
Taiwan Semiconductor Manufacturing Company Limited
G G G
G11C G11C G11C
inventional additional additional
Chia-Hao Geng-Cing Yu-Hao Yi-Tzu Hao-I Cheng-Jen
Hsu Lin Hu Chen Yang Chang