Sheridan Ross P.C.
Memory device, memory system, and memory control method
A memory device of one embodiment of the technology includes: a plurality of memory cells in a matrix arrangement; a plurality of row wirings each coupled to one end of each memory cell; a plurality of column wirings each coupled to another end of each memory cell, a first decoder circuit coupled to each of the row wirings of even-numbered rows; a second decoder circuit coupled to each of the row wirings of odd-numbered rows; a third decoder circuit coupled to each of the column wirings of even-numbered columns; and a fourth decoder circuit coupled to each of the column wirings of odd-numbered columns. The first decoder circuit, the second decoder circuit, the third decoder circuit, and the fourth decoder circuit are constituted by independent circuits from one another.
Sony Semiconductor Solutions Corporation
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Yotaro Haruhiko Makoto
Mori Terada Kitagawa