Myers Bigel Sibley & Sajovec
Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon
Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.
Infineon Technologies AG Chartered Semiconductor Manufacturing, Ltd. Samsung Electronics Co., Ltd. International Business Machines Corporation
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Johnny Min-ho Sang-jine O-sung Thomas W. Jun-jung Sunfei
Widodo Lee Park Kwon Dyer Kim Fang