McClure, Qualey & Rodack, LLP
Method for reducing core-to-core mismatches in SOC applications
Methods for reducing core-to-core mismatch are provided. The method includes measuring gate lengths of a representative pattern of each core in a first lot of SOC products by a measurement apparatus. Each of the SOC products in the first lot includes more than two cores identical to each other. The method also includes determining a tuning amount according to the differences between the gate lengths of each core, and adjusting at least one mask for critical dimensions of gate length of each core in a second lot of SOC products respectively according to the tuning amounts.
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H H
H01L H01L
inventional inventional
Chia-Ming Shih-Che Sheng-Tang Chao-Jui
Chang Lin Wang Wang