Haynes and Boone, LLP
Double patterning methodology
Provided is a method of fabricating a semiconductor device. The method includes providing an integrated circuit layout plan, the integrated circuit layout plan containing a plurality of semiconductor features. The method includes selecting a subset of the features for decomposition as part of a double patterning process. The method includes designating a relationship between at least a first feature and a second feature of the subset of the features. The relationship dictates whether the first and second features are assigned to a same photomask or separate photomasks. The designating is carried out using a pseudo feature that is part of the layout plan but does not appear on a photomask. The method may further include a double patterning conflict check process, which may include an odd-loop check process.
Taiwan Semiconductor Manufacturing Company, Ltd.
G G G
G03F G03F G06F
inventional inventional inventional
Jhih-Jian Cheng Kun Ru-Gun Ken-Hsien Wen-Chun Huang-Yu Tsong-Hua
Wang Tsai Liu Hsieh Huang Chen Ou