Staas & Halsey LLP
LSI layout method and apparatus for cell arrangement in which timing is prioritized
In a layout method for an LSI having a plurality of cells, automated arrangement of cells is performed on the basis of a netlist, which has cells and connection data therefor, and timing conditions, and, once a timing optimization processing is performed so that a plurality of cells are arranged on a chip, global wiring processing is implemented and the wiring congestion rate is analyzed. In addition, in small regions where a wiring congestion rate is so high that detailed wiring processing is judged to be difficult, cell rearrangement processing is implemented. Next, detailed wiring processing is performed with respect to the cells which have been rearranged. The rearrangement of cells is performed only in small regions with a high congestion rate, with the result that the overall cell arrangement in which timing is optimized is not changed markedly, whereby it is possible to reduce the probability of wiring being impossible in the course of the detailed wiring processing.
Fujitsu Limited
G
G06F
inventional
Masayuki Mitsuaki Hiroyuki Kenji Kenji Toshio Daisuke Shuji
Okamoto Nagasaka Honda Yoshida Kobayashi Arakawa Miura Yoshida