Tung & Associates
Multi-layer gate for TFT and method of fabrication
A method for fabricating a thin film transistor that has a multi-layered gate structure of large thickness and the transistors formed are disclosed. In the method, an organic polymeric material layer is spin-coated to planarize a metal gate that has a second metal material deposited in a thin layer on the gate. A suitable metal coating material is molybdenum. A novel planarization process by dry etching is then carried out utilizing a UV spectrum of Mo in an end point detection method to remove all the organic polymeric material from a top planar surface of the metal gate (and the metal coating layer) and then stopping the dry etching process. A dielectric material layer such as silicon nitride is then deposited on top of the metal gate and the remaining organic polymeric material layer to complete the isolation process for the gate. The present invention novel method of utilizing an additional metal coating layer on the metal gate therefore allows an easy identification of the end point in the planarization process wherein an organic polymeric material layer provides a base for depositing a dielectric material thereon for insulating the metal gate. Problems normally associated with the conventional method of insulating a thick metal gate, such as step coverage and void formation problems are thus eliminated in the present invention method.
Industrial Technology Research Institute
H H H
H01L H01L H01L
inventional inventional inventional
Jeng-Hung Tinghui
Sun Huang