Marshall, Gerstein & Borun LLP
Semiconductor memory test device
A semiconductor memory test device configured to reduce level variations of a core voltage and a pumping voltage by shorting an external power voltage and the pumping voltage according to input of a test signal in an operation life test or a burn-in test, and to control levels of the core voltage and a peri voltage according to a level of the external power voltage is disclosed herein. As a result, the semiconductor memory test device is configured to obtain a sufficient margin of the external power voltage and to adaptively transmit a stress voltage to 2.5 V/3.3 V DRAM.
Hynix Semiconductor Inc.
G G
G11C G11C
inventional inventional
Jun Gi Kang Seol
Choi Lee