Multithreaded processor with plurality of scoreboards each issuing to plurality of pipelines
A multi-threaded microprocessor for processing instructions in single threaded mode and multithreaded modes. The microprocessor includes instruction dependency scoreboards, instruction input coupling circuits for selectively feeding the first and second instruction dependency scoreboards; output coupling logic having first and second instruction issue outputs; first and second execute pipelines respectively coupled to the instruction issue outputs, the first execute pipeline for executing a first program thread and the second execute pipeline for executing a second program thread, independent of the first program thread; and a control logic circuit for causing dual issue of instructions from the first program thread, by the first dependency scoreboard, to both the first execute pipeline and said second execute pipeline.
Texas Instruments Incorporated
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