WPAT PC
ESD protection circuit and display apparatus using the same
An ESD protection circuit comprises three transistors and two voltage dividers. The two source/drain terminals of a first transistor are electrically coupled to a first power line and a second power line respectively. The two source/drain terminals of a second transistor are electrically coupled to the first power line and a gate terminal of the first transistor respectively. The two source/drain terminals of a third transistor are electrically coupled to the gate terminal of the first transistor and the second power line respectively. A first voltage divider supplies a first voltage to a gate terminal of the second transistor according to a potential difference between the first power line and the second power line. A second voltage divider supplies a second voltage to a gate terminal of the third transistor according to the potential difference between the first power line and the second power line.
Au Optronics Corp.
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additional additional inventional
Chia-Sheng Yung-Chih Chih-Lung
Li Chen Lin