Volentine & Whitt, PLLC
Clock synchronization circuit and semiconductor memory device including clock synchronization circuit
A clock synchronization circuit includes a delay-locked loop (DLL) and a delay-locked control unit. The DLL is configured to generate an output clock signal by delaying an input clock signal by a delay time, and to execute a delay-locking operation in which the delay time is adjusted to a locked state according to a comparison between the output clock signal and the input clock signal. The delay-locked control unit configured to detect the locked state of the DLL, and to control the DLL based on the determined locked state.
Samsung Electronics Co., Ltd.
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Jung-Hwan Seok-Hun Seong-Hwan Yang-Ki
Choi Hyun Jeon Kim