Christopher P. Maiorana, P.C.
High speed FIFO synchronous programmable full and empty flag generation
An apparatus comprising a flag generation circuit configured to generate an empty flag signal in response to (i) a read clock, (ii) a write clock and (iii) a look ahead bitwise comparison configured to detect when a write count signal minus a read count signal is equal to 1.
Cypress Semiconductor Corp.
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G06F G06F
additional inventional
Johnie Chia Jen Parinda
Au Chang Mekara