Haynes and Boone, LLP
Resistive memory cell array with top electrode bit line
A method for forming a resistive memory cell within a memory array includes forming a patterned stopping layer on a first metal layer formed on a substrate and forming a bottom electrode into features of the patterned stopping layer. The method further includes forming a resistive memory layer. The resistive memory layer includes a metal oxide layer and a top electrode layer. The method further includes patterning the resistive memory layer so that the top electrode layer acts as a bit line within the memory array and a top electrode of the resistive memory cell.
Taiwan Semiconductor Manfacturing Company, Ltd.
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Yu-Wen Hsia-Wei Chih-Yang Kuo-Chi Chin-Chieh Wen-Ting
Liao Chen Chang Tu Yang Chu