Haynes Beffel & Wolfeld LLP
Parallel threshold voltage margin search for MLC memory application
A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes to determine the Vt range(s) that provides matching sum codes. Multiple read voltage margins (i.e. the read voltage margins between multiple programming levels of the MLC memory array) are determined in a parallel fashion as Vt is stepped across its range.
Macronix International Co., Ltd.
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Cheng-Chi Chun Hsiung Kuen-Long Wen Chiao Chin Hung
Liu Hung Chang Ho Chang