Semiconductor memory device and a semiconductor integrated circuit
 A semiconductor memory device which can reduce a power consumption by reducing a charging and discharging current for a gate capacity of a transistor used for pulling up a bit line which constitutes a write recovery circuit. A pair of first and second bit lines are connected to a memory cell. A potential of one of the first and second bit lines is decreased during a write cycle in accordance with write data. A first loading element is connected between a power source line and the first bit line. The power source line supplies a positive power source voltage. A second loading element is connected between the power source line and the second bit line. A first transistor is provided for pulling up the first bit line. The first transistor has a current input terminal connected to the power source line and a current output terminal connected to the first bit line. A second transistor is provided for pulling up the second bit line. The second transistor has a current input terminal connected to the power source line and a current output terminal connected to the second bit line. A transistor drive circuit drives, during a write recovery period, one of the first transistor and the second transistor which is connected to one of the first bit line and the second bit line which is set to a lower potential. 
G
G11C
inventional
Shoichiro Makoto Toshihiko
Kawashima Hamaminato Mori