McDermott Will & Emery LLP
Semiconductor memory device, and read method and read circuit for the same
In a semiconductor memory device operative to discharge residual charge in a read bit line in a read cycle, the bit line is in the reset state at all times except during read operation. The reset state of a bit line is canceled when selected and connected to a read circuit for read, and information stored in a selected memory cell is read via the selected bit line. Upon completion of the read of the memory cell, the selected bit line is disconnected from the read circuit and reset to thereby complete discharge of residual charge in the read bit line prior to read operation in the next cycle. This ensures that during read determination operation in the next read cycle, the potential of a selected bit line will not vary with the bit line residual discharge in the previous read cycle.
Panasonic Corporation
G G
G11C G11C
inventional inventional
Toshiki
Mori