Katten Muchin Zavis Rosenman
Embedding parasitic model for pi-fet layouts
A model for a semiconductor device and more particularly to a Pi-FET with multiple gate fingers. The model takes into account various parasitics and the inter-relationship therebetween. In particular, multi-finger Pi-FETs are modeled as multiple single finger unit cells. Each single unit cell takes into account off-mesa parasitics, inter-electrode parasitics, on-mesa parasitics and includes an intrinsic model which represents the physics that predominantly determine FET performance. As such, the model can be used for relativity accurate device technology modeling, optimization of device performance and device design.
TRW Inc.
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Roger S.
Tsai