Volentine Francos, PLLC
Semiconductor memory circuit
A memory circuit includes a plurality of word lines connected to a plurality of memory cells, a plurality of row address decode circuits having address input terminals, a first wafer burn-in signal terminal, and a second wafer burn-in signal terminal. The row address decode circuits activate all of the word lines when the first wafer burn-in signal and the second wafer burn-in signal are in an enable state. On the other hand, the row address decode circuits activate a subset of the word lines when the second wafer burn-in signal is in the enable state.
Oki Electric Industry Co., Ltd.
G G G
G11C G11C G11C
inventional inventional inventional
Nobuyuki Hitoshi Yoshimasa
Endo Yamada Sekino