MOS Analog switch driven by complementary, minimally skewed clock signals
 An MOS analog switch utilizing two transmission gates which are compensated by a third transmission gate is provided. The transmission gates may be either single or complementary conductivity type transmission gates and are controlled by complementary clock signals. A method and apparatus for minimizing clock skew thereby reducing error voltages caused by parasitic capacitance are provided. 
Motorola, Inc.
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inventional inventional
Joe W. Roger A. Robert N.
Peterson Whatley Allgood