Ladas & Parry
Method for scanning keypad architecutre employing power source and ground of digital electronic devices
 A scanning method of keypad architectures utilizing power pin V.sub.DD and ground pin GND of an integrated circuit device is disclosed. The integrated circuit device has a number of row pins and column pins, a power pin and a ground pin, and a number of pins for other functions of the integrated circuit device. The row and column pins, power pin and ground pin of the integrated circuit device are connected to respective connections of a keyswitch matrix, which has a plurality of row connections and column connections. The keyswitch matrix of the scanning apparatus has a first one of the row connections connected to the power pin. The keyswitch matrix of the scanning apparatus has a second one of the row connection connected to the ground pin. Each of the other row pins is connected respectively to corresponding one of the row connections. Each of the column pins is connected respectively to corresponding one of the column connections. The scanning scheme is employed to identify the row and column of the key having its key switch depressed. A keyswitch matrix having a total of (M-2)+(N-2) integrated circuit device pins can have a maximum of (M.times.N)-4 keys in the keypad. 
United Microelectronics Corporation
H
H03M
inventional
Chun-Yen
Chang