Memory layout structure
A memory layout structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with all storage units on a corresponding active area, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.
UNITED MICROELECTRONICS CORP.
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Po-Kai Hung-Yueh Yu-Ping Hui-Lin Jing-Yin Kun-I
Hsu Chen Wang Wang Jhang Chou