Integrated circuit having buffering circuitry with slew rate control
 Buffering circuitry (10) uses pull-up slew rate control circuitry (12) and pull-down slew rate control circuitry (14) to control the rising and falling slew rates of an output signal (50) provided by buffering circuitry (10). Pull-up slew rate control circuitry (12) and pull-down slew rate control circuitry (14) may be used in an embodiment of buffering circuitry (10) which provides a higher output voltage VHIGH than the standard power voltage VPOWER which is used to power most of the circuitry. Buffering circuitry (10) utilizes distributed resistive elements (89-91) to provide improved electrostatic discharge protection. Buffering circuitry (10) utilizes a low power level shifter (16). Voltage reference generation circuitry (18) may be used to provide a stable low power reference voltage VREF (42). 
Motorola, Inc.
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G05F H03K H03K
inventional inventional inventional
Roger A. Bernard J.
Whatley Pappert