Haynes and Boone, LLP
Integration of magneto-resistive random access memory and capacitor
The present disclosure provides one embodiment of a semiconductor structure that includes a first metal layer formed on a semiconductor substrate, wherein the first metal layer includes a first metal feature in a first region and a second metal feature in a second region; a second metal layer disposed on the first metal layer, wherein the second metal layer includes a third metal feature in the first region and a fourth metal feature in a second region; a magneto-resistive memory device sandwiched between the first metal feature and the third metal feature; and a capacitor sandwiched between the second metal feature and the fourth metal feature.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
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additional inventional inventional
Chung-Cheng Tien-Wei Ya-Chen
Chou Chiang Kao