Seyfarth Shaw LLP
Wafer level processing method and structure to manufacture two kinds of interconnects, gold and solder, on one wafer
A chip structure comprising a substrate, a plurality of wire bonding pads and a plurality of solder pads is provided. Gold bumps or gold pads can be formed on the wire bonding pads while solder bumps can be formed on the solder pads concurrently. Alternatively, both wire bonding pads and solder pads can be formed of the same metal stack.
Megit Acquisition Corp.
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Chu-Fu Chien-Kang Li-Ren Chiu-Ming
Lin Chou Lin Chou