Duane Morris LLP
Scan architecture for interconnect testing in 3D integrated circuits
A device comprises a first die; and a second die stacked below the first die with interconnections between the first die and the second die. A least one of the first die or the second die has a circuit for performing a function and provides a functional path. Each of the first and second dies comprise a plurality of latches, including a respective latch corresponding to each one of the interconnections; and a plurality of multiplexers. Each multiplexer is connected to a respective one of the plurality of latches and arranged for receiving and selecting one of a scan test pattern or a signal from the functional path for outputting during a scan chain test of the first die and second die.
Taiwan Semiconductor Manufacturing Co., Ltd.
G G G G G G G G
G01R G01R G01R G01R G01R G01R G01R G01R
inventional inventional inventional inventional inventional inventional inventional inventional
Sandeep Kumar Marat Saman M. I. Yun-Han
Goel Gershoig Adham Lee