Haynes and Boone, LLP
FinFET fabrication methods
A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.
Taiwan Semiconductor Manufacturing Co., Ltd.
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inventional inventional inventional inventional inventional inventional additional additional inventional inventional inventional inventional inventional additional inventional inventional inventional inventional inventional inventional inventional additional inventional inventional
Kuo-Feng Yin-Pin Cheng-Yi Da-Wen Jian-Hao Shahaji B. Chun Hsiung
Yu Wang Peng Lin Chen More Tsai