Phase locked loop for controlling a recording device and method thereof
A PLL system for generating an output signal according to a first reference signal is disclosed. The PLL system includes a clock generator to generate the output signal according to a phase difference between the first reference signal and the frequency-divided signal; and a phase-shift detector for detecting a position difference between the physical address and an updated logical address of the recording data to generate a phase adjusting signal. The PLL system also includes an adder for updating a detected logical address with a random value to output the updated logical address to the position difference detector; and a phase-controllable frequency divider for generating the frequency-divided signal and for receiving the phase adjusting signal to adjust the phase of the frequency-divided signal.
Mediatek Inc.
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Hong-Ching Chi-Ming Chin-Ling
Chen Chang Hung