Duane Morris LLP
IC degradation management circuit, system and method
An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.
Taiwan Semiconductor Manufacturing Co., Ltd.
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Wen-Shen Po-Zeng Yung-Chow Chih-Hsien
Chou Kang Peng Chang