Koppel, Patrick, Heybl & Philpott
Semiconductor device and manufacturing method thereof
A Si-on-half-insulator device and its manufacturing method are disclosed in this invention. In one embodiment, a horizontal insulating layer located below at least one of the source and drain regions is realized to reduce junction capacitance. In another embodiment, a horizontal insulating layer located below at least one of the source and drain regions and a vertical insulating layer located below at least one side surface of the gate are realized. The additional vertical insulating layer can reduce punch leakage. Further, a method of manufacturing the above semiconductor device is also disclosed, wherein the horizontal and vertical insulating layers are formed using an additional layer of epitaxially grown semiconductor material and isolating trenches.
Semiconductor Manufacturing International (Beijing) Corporation
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Jinhua
Liu