Perkins Coie LLP
Memory device with a latching mechanism
A memory device includes a timing circuit configured to: receive an input signal, wherein the input signal is one signal within a group of input signals (e.g., multiple bits or nibbles) that are communicated according to a sequence with each of the input signals individually in serial to parallel operations, and generate a grouped latching timing signal based on the received input signal, wherein the timing signal corresponds to nibbles of the data.
Micron Technology, Inc.
G G G G G G G G G G
G11C G11C G11C G11C G11C G11C G11C G11C G11C G11C
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Vijayakrishna J. Michael V.
Vankayala Ho