Haynes and Boone, LLP
Field effect transistor contact with reduced contact resistance
The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
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Chung-Ting Chien-Hao Chih-Wei Ziwei Yan-Ming Su-Hao Huicheng
Wei Chen Chang Fang Tsai Liu Chang