Oliff & Berridge, PLC
Layered chip package
A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed.
Headway Technologies, Inc. TDK Corporation
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Hiroyuki Satoru Nobuyuki Yoshitaka Tatsuya
Ito Sueki Okuzawa Sasaki Harada