Array multiplier adapted for tiled layout by silicon compiler
 An array multiplier using modified Booth encoding of multiplier input signals is formed on the surface of a monolithic integrated circuit using masks generated by a computer, in accordance with a silicon compiler program, by arranging an array of standard cells selected from a library of standard cell designs in a tessellation procedure. The array multiplier is laid out in accordance with one of particular tessellation patterns, which employ simpler and more regular patterns of interconnections between cells. Carry-save addition is used in combining partial product terms to avoid concatenating long ripple carry times. 
General Electric Company
G
G06F
inventional
Michael J. Chi-Yuan Chung-Yih Kenneth B. Richard I.
Hartman Chin Ho Welles, II Hartley