Schwegman Lundberg & Woessner, P.A.
Routing framework to resolve single-entry constraint violations for integrated circuit designs
Aspects of the present disclosure address improved systems and methods for resolving single-entry constraint violations in hierarchical integrated circuit designs. In routing multi-pin nets of IC designs, the system employs a partition-entry-aware search algorithm to identify single-entry-violation-free routing results for two-pin nets, which are then combined to form routed multi-pin nets. The search algorithm is “entry-aware” in that it penalizes multiple entries into a single partition. Consistent with some embodiments, the system may further employ a post fix stage to remove extra partition entries for the multi-pin nets with single-entry violations by choosing a main entry to enter a partition and rerouting the paths that cause the violations such that the paths share the main entry.
Cadence Design Systems, Inc.
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Wen-Hao Wing-Kai Mehmet Can Zhuo Gracieli
Liu Chow Yildiz Li Posser