Method and apparatus for reducing clock signal power consumption within an integrated circuit
A method is provided whereby a placement-based cost function is utilized to minimize leakage and dynamic power that is consumed by clock networks implemented within integrated circuits (ICs) such as field programmable gate arrays (FPGAs). An initial placement of clock signal loads is analyzed to determine whether an alternative placement of clock signal loads results in the reduction of the usage of vertical clock spines, or equivalently, the optimization of the cost function. Several desirable characteristics are obtained through strategic clock signal load placement within the FPGA in accordance with the cost function. First, the number of clock regions spanned by a particular clock signal is minimized. Second, interconnect capacitance within the clock region is also minimized. By minimizing the total capacitance of a particular clock network implemented within a clock region, the leakage and dynamic power consumed by the clock network within the clock region is also minimized.
Xilinx, Inc.
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Subodh Qiang Jason H.
Gupta Wang Anderson