Jianq Chyun IP Office
Resistive memory apparatus and writing method thereof
A resistive memory apparatus and a writing method thereof are provided. In the method, logic data is received, and a corresponding resistive memory cell is selected. A logic level of the logic data is determined. When the logic data is in a first logic level, where a first reading current of the corresponding resistive memory cell is greater than a first reference current, a set pulse and a reset pulse are provided to the resistive memory cell during a writing period. When the logic data is in a second logic level, where a second reading current of the resistive memory cell is smaller than a second reference current, the reset pulse is provided to the resistive memory cell during the writing period. Polarities of the reset pulse and the set pulse are opposite.
Winbond Electronics Corp.
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Frederick Shao-Ching Chuan-Sheng Ping-Kun Meng-Hung
Chen Liao Chou Wang Lin