Nicholson De Vos Webster & Elliott, LLP
Test, validation, and debug architecture
An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.
INTEL CORPORATION
G G
G06F G06F
inventional inventional
Yuen Tat Selvakumar Raja Arun R. Nagib Z. Lyle E. Russell J. Mark B. Abhijit Priyadarsan Wee Hoo Keith Rahima K. Padmakumar Ridvan A. Christian E. Edwin E. Brian Yi Amy Travis K. Tieyu Evan J. Vui Yong William H. Timothy S. David C. Kapila B. John L. Samie B. Mukesh Ashok N. Bruce Jiun Long Kyle Hermann W. Loren J. David W. James J. Kip C. Neil Chinna B. Jay J. Keshavan K. Sanjay S.
Lee Gopal Ramadorai Hakim Cool Wunderlich Trobough Davare Patra Cheah Drescher Mohammed Gopal Sahan Iovin Parks Meyer Xia Goff Zheng Halprin Liew Penner Storey Florey Udawatta Baudrexl Samaan Kataria Kabadi Querbach Foo Markley Gartler McConnell Grawrock Grealish Killpack Dobler Prudvi Nejedlo Tiruvallur Salem