Morgan, Lewis & Bockius LLP
Delay locked loop circuitry for clock delay adjustment
A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.
Rambus Inc.
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Leung Kevin S. Jun Donald C. Bruno W. Yiu-Fai Nhat M. Mark G. Chanh Vi Benedict C. Pak Shing Thomas H. Mark A.
Yu Donnelly Kim Stark Garlepp Chan Nguyen Johnson Tran Lau Chau Lee Horowitz