Jaffery, Watson, Mondonsa & Hamilton LLP
Dynamic thread execution arbitration
A mechanism is described for facilitating thread execution arbitration for thread scheduling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes assigning priority levels to threads based on stall signals communicated from the one or more shared function units to one or more execution units of a processor including a graphics processor, and selecting a first thread to be scheduled and a second thread to be ignored based on the stall signals.
INTEL CORPORATION
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Subramaniam M. Balaji Eric J. Altug Abhishek R. Prasoonkumar Joydeep
Maiyuran Vembu Hoekstra Koker Appu Surti Ray