Myers Bigel Sibley & Sajovec, P. A.
Methods of operating memory devices including negative incremental step pulse programming and related devices
A memory device may include a plurality of memory cell transistors serially coupled in a string between a string selection transistor and a ground selection transistor. Moreover, the string selection transistor may be coupled between the string and a bitline, and the ground selection transistor may be coupled between the string and a common source line. During programming, one of the plurality of memory cell transistors in the string may be selected for a program operation so that other memory cell transistors in the string are unselected, and a plurality of negative voltage pulses may be applied to a channel region of the selected memory cell transistor. While applying the plurality of negative voltage pulses to the channel region, a positive pass voltage may be applied to control gate electrodes of the unselected memory cell transistors, and a positive program voltage may be applied to a control gate electrode of the selected memory cell. Related methods and devices are discussed.
Samsung Electronics Co., Ltd.
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Seungwon
Lee