Method to erase a flash EEPROM using negative gate source erase followed by a high negative gate erase
 A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by first applying a moderately high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a first relatively large negative voltage is applied to the control gate. While a ground reference potential is applied to the semiconductor substrate. At this same time the drain is floating. The flash EEPROM cell is then detrapped by floating the source and drain and applying the ground reference potential to the semiconductor substrate. At the same time a second relatively large negative voltage pulse is applied to the control gate. 
Taiwan Semiconductor Manufacturing Company, Ltd.
G
G11C
inventional
Kuo-Reay Juang-Ke Jian-Hsing Ming-Chou
Peng Yeh Lee Ho