Jaffery Watson Mendonsa & Hamilton LLP
Instructions and logic to perform floating-point and integer operations for machine learning
One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.
Intel Corporation
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Vasanth Kamal Abhishek R. Xiaoming Anbang Joydeep Altug Balaji Tsung-Han Sanjeev Ping T. Nicolas C. Mark A. Rajkishore Sanu K. Eriko Michael S. Tatiana Himanshu
Ranganathan Sinha Appu Chen Yao Ray Koker Vembu Lin Jahagirdar Tang Galoppo Von Borries Anders Barik Mathew Nurvitadhi Strickland Shpeisman Kaul