Lowe Hauptman & Ham, LLP
Decomposing integrated circuit layout
Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed.
Taiwan Semiconductor Manufacturing Company, Ltd.
G
G06F
inventional
Tsai-Sheng Gwan Sin Yung-Sung Ken-Hsien Ming-Hui Pi-Tsung Wen-Chun Wen-Ju Wei-Long Ru-Gun
Gau Chang Yen Hsieh Chih Chen Huang Yang Wang Liu