Fay, Sharpe, Beall, Fagan, Minnich & McKee
Semiconductor integrated circuit
 A rate conversion circuit area (8) is provided between a spread gate area (4) which operates in synchronization with a clock signal CLK and a RAM core (7) (macro cell) operating in synchronization with a clock signal (ck) whose frequency is higher than that of the clock signal (CLK). With this arrangement, the single port core is made accessible as a dual port RAM by forming the clock signal (ck) whose frequency is multiplied an optional number of times that of the clock signal (CLK), receiving access data equivalent to a plurality of operating cycles in parallel from the spread gate area during a predetermined unit operating access cycle period in the spread gate area, and serially supplying these to the RAM core 7 during the plurality of operating cycle periods in synchronization with the clock signal (ck). 
Hitachi ULSI Engineering Corp. Hitachi, Ltd.
G
G11C
inventional
Satoshi Yoichi Masao Takahiko
Shinagawa Sato Mizukami Kozaki