J.C. Patents
Pseudo bipolar junction transistor
 A pseudo bipolar junction transistor according to the invention includes two MOS transistors operating in saturation region, electrically connected in parallel with their drains and sources functioning as a collector and a emitter of the pseudo bipolar junction transistor, respectively, a first gate without any signal inputted and a second gate functioning as a base of the pseudo bipolar junction transistor, wherein the two gates is supplied with the same DC bias. The pseudo bipolar junction transistor is manufactured by CMOS process for applications in variable gain amplifiers, transfer linear function signal processors and logarithmic filters. 
National Science Council
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Cheng-Chieh Shen-Iuan
Chang Liu