Jaffery Watson Mendonsa & Hamilton LLC
Memory access compression using clear code for tile pixels
One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is cleared to a clear color and a graphics pipeline module to bypass a memory access for the first virtual page based on the first page table entry.
Intel Corporation
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Prasoonkumar Abhishek R. Kiran C.
Surti Appu Veernapu