IP & T Group LLP
Storage device and operating method thereof
A memory controller having improved read performance controls a memory device including a plurality of memory cells. The memory controller includes a read operation controller, a history bias storage, and a read voltage setting circuit. The read operation controller read data stored selected memory cells among the plurality of memory cells. The history bias storage stores a plurality of history mean biases, which are mean biases of a plurality of threshold voltage distributions that the plurality of memory cells have, and a plurality of reference cell count values respectively corresponding to the plurality of threshold voltage distributions.
SK hynix Inc.
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G11C G11C G11C G11C G11C G11C G06F G06F G11C G11C
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Seon Ju Min Hwan
Lee Moon