Baker & McKenzie LLP
Systems and methods for trimming control transistors for 3D NAND flash
Control transistors and memory cells within 3D NAND Flash memory arrays may both be created using the same technology, such as charge trapping structures, to simplify the fabrication process. However, the resulting control transistors may initially have higher variability in threshold voltages, when compared to traditional gate-oxide-based control transistors. Provided are exemplary techniques to trim control transistors to provide increased reliability and performance during array operation.
MACRONIX INTERNATIONAL CO., LTD.
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Hang-Ting Chih-Shen Kuo Pin
Lue Chang Chang