F. Chau & Associates, LLP
Clock synchronization circuit and semiconductor device having the same
A clock synchronization circuit is provided for synchronizing an external clock signal with an internal clock signal. The circuit is connected to a clock buffer adapted to output the internal clock signal. The circuit includes a first loop adapted to receive the external clock signal and output a plurality of reference clock signals having a predetermined phase difference therebetween. A second loop is adapted to delay the plurality of reference clock signals; select a signal from among the plurality of delayed reference clock signals; provide the selected signal to the clock buffer; detect a phase difference between the internal clock signal output from the clock buffer and the external clock signal; generate a plurality of control voltages to reduce the detected phase difference, and control a delay amount of each of the plurality of reference clock signals in response to the plurality of control voltages; so as to synchronize the internal clock signal with the external clock signal.
Samsung Electronics Co., Ltd.
H H H G G G G
H03L H03L H03L G11C G11C G06F G11C
inventional inventional inventional inventional inventional inventional inventional
Dae-yun Yeon-jae Seung-wook Won-chan
Shim Jung Lee Kim