Nikolai & Mersereau, P.A.
Method on scan chain reordering for lowering VLSI power consumption
A method for reordering a scan chain meets given constraints and minimizes peak power dissipation. The given constraints include a maximum peak power dissipation, a maximum scan chain length and a maximum distance between two successive registers. The method includes embedding a developed tool into an existing VLSI design flow for low-power circuit designs. Furthermore, the characteristics quickly judge if the problem has corresponding feasible solutions and searching the optimal solution. Modified data from the given scan chain declaration data and the scan pattern data, which satisfy the constraints, can be obtained.
Chang Gung University
G G
G01R G01R
inventional inventional
Chia-Chi Chia-Ming Herng-Jer Wu-Shiung
Chu Ho Lee Feng