J.C. Patents
Low power programmable logic array assembly
An assembling method for a low-power programmable logic array circuit. The assembling method is capable of reducing delays and unnecessary power consumption. According to the low potential power loss when the dynamic gates in the AND-plane and the OR-plane output a low potential, the high potential power loss when the dynamic gates in the AND-plane and the OR-plane output a high potential and the probability of the dynamic gates outputting a high potential, a selection between new dynamic logic circuit and conventional dynamic circuit is carried out. The conventional dynamic circuit in the AND-plane refers to a conventional dynamic circuit whereas the conventional dynamic circuit in the OR-plane refers to a conventional footless dynamic circuit
National Chung Cheng University
H
H03K
inventional
Ching-Wei Ching-Rong Jinn-Shyan
Yeh Chang Wang