Finch & Maloney PLLC
Techniques for controlling transistor sub-fin leakage
Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.
INTEL Corporation
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Karthik Glenn A. Gopinath Heidi M. Daniel B. Anand S. Tahir Prashant
Jambunathan Glass Bhimarasetti Meyer Aubertine Murthy Ghani Majhi