Withrow & Terranova, PLLC
Bi-stable static random access memory (SRAM) bit cells formed from III-V compounds and configured to achieve higher operating speeds
Bi-stable static random access memory (SRAM) bit cells formed from III-V compounds and configured to achieve higher operating speeds are disclosed. In one aspect, a bi-stable SRAM bit cell includes substrate, first well layer formed over substrate from a III-V compound doped with a first type material, and second well layer formed over first well layer from a III-V compound doped with a second type material. Channel layer is formed over second well layer from a III-V compound doped with the first type material. Source and drain regions are formed over channel layer from a III-V compound doped with the first type material, and gate region is formed over channel layer. Bipolar junction transistors (BJTs) are formed such that a data value can be stored in second well layer. Collector tap electrode is configured to provide access to collector of each BJT for reading or writing data.
QUALCOMM Incorporated
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inventional inventional additional inventional inventional inventional inventional inventional additional inventional inventional inventional inventional inventional inventional inventional inventional additional inventional inventional inventional inventional inventional inventional inventional inventional
Bin Xia Gengming
Yang Li Tao