Integrated circuit embedded with single-poly non-volatile memory
A system on chip (SOC) contains a core circuit and an input/output (I/O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a single-poly floating gate, a first P+ doped drain region and a first P+ doped source region, the second PMOS transistor includes a single-poly select gate and a second P+ doped source region, and the first P+ doped source region of the first PMOS transistor serves as a drain of the second PMOS transistor.
eMemory Technology Inc.
G H G H
G11C H01L G11C H01L
inventional inventional additional inventional
Ming-Chou Shih-Jye Ching-Hsiang Chih-Hsun
Ho Shen Hsu Chu