Myers Bigel Sibley & Sajovec
Methods of manufacturing integrated circuit capacitors having hemispherical grain electrodes
Methods of manufacturing integrated circuit capacitors include the steps of forming a first electrically insulating layer having an opening therein, on a semiconductor substrate and then forming an electrically conductive electrode layer on an upper surface of the first electrically insulating layer and on a sidewall of the opening within the first electrically insulating layer. The electrically conductive electrode layer is then covered with a second electrically insulating layer. The second electrically insulating layer and the electrically conductive electrode layer are then planarized to expose the upper surface of the first electrically insulating layer and define a capacitor electrode layer on the sidewall of the opening. The capacitor electrode layer is then selectively etched back to expose the sidewall of the opening and define a lower capacitor electrode that is recessed relative to the upper surface of the first electrically insulating layer. This etching step is performed using the planarized second electrically insulating layer and the first electrically insulating layer as an etching mask. The planarized second electrically insulating layer and the upper surface of the first electrically insulating layer are then removed to expose the lower capacitor electrode. Hemispherical silicon grains (HSGs) are formed on an inner surface of the exposed lower capacitor electrode.
Samsung Electronics Co., Ltd.
H H
H01L H01L
additional inventional
Jae-soon Ki-yeon Seung-hwan
Lim Park Lee