Sampling clock phase correction circuit of video signal
 A sampling clock phase correction circuit of video signal to keep stably a phase of a sampling clock to an image signal. A delayed signal of a video sync signal is employed for a reference signal of a sampling clock generation circuit. The delay quantity of the video sync signal is controlled to sample stably the video image signal according to the comparison and discrimination of a phase relation between a sampling clock signal and a video sync signal by a phase detection circuit and a CPU circuit. A precise phase correction where a characteristic change of circuit elements by a temperature drift or the like is compensated can be attained even for a high frequency video signal exceeding 100 MHz. 
Seiko Instruments & Electronics Ltd.
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H03L H04N G06K G06K
inventional inventional additional inventional
Fumihiro Kaneo Yoshio Shinya Kenichi
Tanaka Yamaguchi Shimada Watanabe Matsushima