Myers Bigel Sibley & Sajovec
High burst rate write data paths for integrated circuit memory devices and methods of operating same
Integrated circuit memory devices include a memory cell array that is configured to write N data bits in parallel and a write data path that is configured to serially receive 2N data bits from an external terminal. The write data path includes 2N write data buffers that are configured to store the 2N data bits, 2N switches, and N data lines that are configured to connect at least N of the 2N switches to the memory cell array to write therein N data bits in parallel. A reduced number of local data lines and/or global data lines may be provided.
Samsung Electronics Co., Ltd.
G G G
G11C G11C G11C
additional inventional inventional
One-gyun Yun-sang Sung-ryul Jung-bae
La Lee Kim Lee