IP & T Group LLP
Semiconductor device and memory system having input buffer circuit
Provided is an input buffer circuit comprising a high-voltage protection unit coupled to a pad and comprising a low-voltage pass unit and a high-voltage pass unit that are coupled in common to an output signal node. The low-voltage pass unit may transfer the first voltage to the output signal node, when a first voltage falling within a first voltage range is applied through the pad. The high-voltage pass unit may transfer a third voltage lower than the second voltage to the output signal node, when a second voltage falling within a second voltage range higher than the first voltage range is applied through the pad.
SK hynix Inc.
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G11C G11C G11C H03K G11C G11C G11C G11C
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Seung Ho
Lee