Haynes and Boone, LLP
Cut-mask patterning process for FIN-like field effect transistor (FINFET) device
Disclosed is a mask for use in a lithography system having a defined resolution. The mask comprises first and second patterns that are greater than the defined resolution and a sub-resolution feature that is less than the defined resolution. Portions of the first and second patterns are positioned close to each other and separated by the sub-resolution feature in an intersection area. The size and shape of the sub-resolution feature are such that when the mask is used in the lithography system, a resulting pattern includes the first and second patterns interconnected with each other through the interconnection area.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
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Ching-Yu Wei-De Kuei-Liang Ming-Feng
Chang Ho Lu Shieh