Duane Morris LLP
Test probing structure
A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.
Taiwan Semiconductor Manufacturing Co., Ltd.
G G H
G01R G01R H01L
inventional inventional additional
Mill-Jer Hung-Chih Chin-Chou Sandeep Kumar Yun-Han Chung-Sheng Ching-Fang Chao-Yang
Wang Lin Liu Goel Lee Yuan Chen Yeh