Patterson + Sheridan, LLP
Stacked silicon package assembly having thermal management
A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.
XILINX, INC.
H H H H H H H H H H H H H H H H H H H H H H H H H
H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L
additional inventional additional additional inventional inventional additional additional additional inventional additional additional additional additional inventional additional inventional inventional inventional additional inventional inventional inventional additional inventional
Suresh Henley Cheang-Whang Tien-Yu Gamal Jaspreet Singh Myongseob
Ramalingam Liu Chang Lee Refai-Ahmed Gandhi Kim