Wood, Herron & Evans, LLP
Vertical NPNP structure in a triple well CMOS process
A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.
International Business Machines Corporation
H H H H H
H01L H01L H01L H01L H01L
inventional inventional additional inventional inventional
Rahul Shunhua Kiran V. Junjun John B. Robert J. Mujahid
Mishra Chang Chatty Li Campi, Jr. Gauthier, Jr. Muhammad