McDermott Will & Emery LLP
Processor system, instruction sequence optimization device, and instruction sequence optimization program
To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a flag detecting section detects an assignment control flag and a clock control flag added to instruction code. An instruction assignment controlling section outputs the instruction code to a CPU or an HWE based on the detection to have the instruction code executed. A clock controlling section supplies a clock signal having a frequency lower than the maximum clock frequency to one of the CPU and the HWE in which a waiting time arises when the CPU and the HWE operate at the maximum clock frequencies, thus reducing power consumption.
Panasonic Corporation
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Isao Hiroshi
Tanaka Mizuno