Low energy accelerator processor architecture with short parallel instruction word and non-orthogonal register data file
An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit is coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor is configured to execute instruction words received on the system bus and has a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a non-orthogonal data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.
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Manish Srinivas Johann Seok-Jun
Goel Lingam Zipperer Lee