Jianq Chyun IP Office
Anti-fuse circuit and method for anti-fuse programming and test thereof
An anti-fuse circuit including a plurality of programmable units and a test module is provided. The programmable units receive a stress voltage, a program data, and a write enable signal. During a programming period, the programmable units sequentially transmit the program data. When the write enable signal is enabled, the stress voltage stresses the programmable units according to the program data, and the programmable units output programming results for test. The test module is coupled to the programmable units and receives the program data and the programming results. During a test period, the test module compares the programming results with the program data and outputs different logic levels according to a result of the comparison of the first programming results and the program data. A method for anti-fuse programming and test adapted to the foregoing anti-fuse circuit is also provided.
Elite Semiconductor Memory Technology Inc.
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inventional inventional inventional
Chien-Yi Ming-Chien
Chang Huang