High speed ferroelectric random access memory
For realizing high speed ferroelectric random access memory, bit line is multi-divided for reducing parasitic capacitance, so that the bit line is quickly charged or discharged by a memory cell including a ferroelectric capacitor when reading. Particularly, a non-inverting local sense amp is devised for reducing area, such that the memory cell is read by the local sense amp through a lightly loaded local bit line, and the local sense amp is read by a global sense amp through a global bit line. By the sense amps, a voltage difference in the local bit line is converted to a time difference for differentiating data “1” and data “0”, and buffered data path is used for achieving fast data transfer. Additionally, various alternative circuits and memory cell structures for implanting the memory are described.
G G
G11C G11C
inventional inventional
Juhan
Kim