Choate, Hall & Stewart LLP
Semiconductor device fabrication
There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a first and a second nucleation layer on a substrate; depositing a binary layer over these nucleation layers; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge and their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.
AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
H H H H H H H H H H H H H H H H
H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L
inventional inventional inventional inventional inventional inventional inventional inventional inventional additional inventional additional additional inventional inventional inventional
Lakshmi Kanta Rasanayagam Sivasayan Sudhiranjan Manippady Krishna Surani Bin
Bera Kajen Tripathy Kumar Dolmanan