Arent Fox LLP
Receiving device including packet output circuit for outputting control signal
A clocking circuit of a receiving unit performs a clocking operation synchronously with a network clock. A packet output circuit of the receiving unit outputs a second packet included in a first packet and outputs a control signal indicating normality/abnormality of output timing of the second packet based on a result of comparing a time of the clocking circuit and a time of first time information included in the first packet. A clock adjusting circuit of a processing unit synchronizes, when the second packet includes second time information indicating a time based on a transmitting side reference clock and when the control signal indicates normality, a receiving side reference clock with the transmitting side reference clock based on a result of comparing a time based on the receiving side reference clock and a time of the second time information.
Fujitsu Semiconductor Limited
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inventional inventional inventional inventional
Tatsushi
Otsuka