Routing access with minimized bus area in multi-port memory device
A multi-port memory device includes first and second ports, a first dedicated memory area assigned to the first port, a plurality of shared memory units having shared access by the first and second ports, a first set of I/O lines for the first dedicated memory area, and a second set of I/O lines for the shared memory units with the second set having more I/O lines than the first set. For example, the second set has N times more I/O lines than the first set, with N being a number of ports of the multi-port memory device or with N being a number of shared memory banks in a shared memory area.
Samsung Electronics Co., Ltd.
G
G11C
inventional
Jung-Sik Chi-Sung
Kim Oh