Myers Bigel Sibley & Sajovec
Circuits for block redundancy repair of integrated circuit memory devices
 A memory cell array includes a plurality of memory blocks, each of which includes normal memory cells and spare memory cells, arranged in arrays having rows and columns. A row or column of spare memory cells in one of the memory cell blocks is substituted for a defective row or column of normal memory cells in the one of the memory blocks, without substituting a row or column of spare memory cells in remaining ones of the memory cell blocks for a row or column of normal memory cells in the remaining ones of the memory blocks. Stated differently, a predetermined row or column of spare memory cells in a first one of the memory blocks is substituted for a first defective row or column of normal memory cells in the first one of the memory blocks, and the predetermined row or column of spare memory cells in a second one of the memory blocks is also substituted for a second defective row or column of normal memory cells in a second one of the memory blocks. Thus, a given row or column of spare memory cells can be used to substitute for different rows or columns of memory cells in each memory block. The number of spare memory cells which is required is thereby reduced. 
Samsung Electronics Co., Ltd.
G G
G11C G06T
inventional inventional
Seung-hun
Lee