Ropes & Gray LLP
High-speed serial interface architecture for a programmable logic device
A high-speed serial interface for a programmable logic device includes a plurality of features to handle the various issues that may arise with data rates over 1 Gbps and particularly over 1.25 Gbps. Those features may include dynamic phase alignment to control clock-data skew, data realignment (e.g., bit slip circuitry) to account for channel-to-channel skew, full-duplex serializer and deserializer, out-of-range frequency support for low frequencies, and a soft-CDR mode.
Altera Corporation
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Kwong-Wen Yu Sergey Thungoc M.
Wei Xu Shumarayev Tran