Bever, Hoffman & Harms, LLP
Constraint memory node identification in sequential logic
A method of identifying memory nodes includes reading a netlist of the design. For a sequential cell of the design, constraint arcs between constraint and related pins can be extracted. For each constraint arc, an original vector set including initialization waveforms can be generated. A plurality of simulations can be run using a plurality of vector sets to generate a plurality of node sets. Each simulation generates a corresponding node set that toggles based on waveforms provided by a corresponding vector set. Each vector set is derived from the original vector set. A final set of memory nodes for the sequential circuit cell can be calculated by subtracting one node set from another node set. In one embodiment, the method can further include pruning non-gate connected nodes from the final node set.
Synopsys, Inc.
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Paul Qing Srivathsan Krishna
Frain Zhang Mohan