Duane Morris LLP
Jitter monitoring circuit
A circuit includes: a first delay circuit configured to receive a first clock signal; a second delay circuit configured to receive a second clock signal; a delay control circuit, coupled to the first and second delay circuits, and configured to cause the first and second delay circuits to respectively align the first and second clock signals within a noise window; and a loop control circuit, coupled to the first and second delay circuits, and configured to alternately form a first oscillation loop and a second oscillation loop passing through each of the first and second delay circuits so as to determine the noise window.
Taiwan Semiconductor Manufacturing Co., Ltd.
G H G
G01R H03L G01R
inventional inventional inventional
Tien-Chien
Huang