Ladas & Parry LLP
Wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield and a method for fabricating the same
A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.
SK Hynix Inc.
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Sung Min Seong Cheol Tac Keun Ha Na Sang Joon Chang Jun Kwon Whan Hyeong Seok
Kim Kim Oh Lee Lim Park Han Choi