Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Semiconductor memory device
 In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units. 
Kabushiki Kaisha Toshiba
G G
G11C G11C
inventional inventional
Shinichiro Ken-ichi Yukihito Ryo Takehiro Masako Mitsuo Shigeyoshi
Shiratake Maeda Oowaki Fukuda Hasegawa Yoshida Saito Watanabe