Radiation-hard isoplanar cryo-CMOS process suitable for sub-micron devices
 A radiation-hard isoplanar cryo-CMOS process suitable for submicron device fabrication reduces channel length to submicron levels. A channel stop (52) is formed after a first polysilicon gate (50) is formed to reduce the space between a n-/n+ source/drain region (67, 68) and the channel-stop region (52). Double gate oxidation steps are performed to increase polyoxide thickness. A thermal oxide masking step is carried out to obtain a thin layer of gate oxide under a second polysilicon gate (60A) for CMOS devices. The process includes two different second polysilicon masking steps to provide dimension control of second polysilicon gates (60A) and to remove bridging of the second polysilicon where the second polysilicon layer (58) is over the first polysilicon layer (48). 
Raytheon Company
H H
H01L H01L
inventional inventional
James S. Chen-Chi P.
Cable Chang