Myers Bigel Sibley & Sajovec, P.A.
Systems, devices and methods using redundant error correction code bit storage
A device, e.g., a semiconductor memory device, includes a plurality of memory cells, each configured to store at least one data bit and a plurality of error correction code (ECC) cells configured to redundantly store ECC bits for the memory cells. According to some embodiments, the plurality of ECC cells includes a plurality of pairs of ECC cells configured to store an ECC bit and a complement thereof. According to further embodiments, the plurality of ECC cells includes a plurality of groups of at least three ECC cells configured to store identical copies of an ECC bit.
Samsung Electronics Co., Ltd.
G G
G11C G06F
additional inventional
Hyun Ho Chul Woo Sang Beom Ho Jung
Choi Park Kang Kim