J.C. Patents
Clock gate buffering circuit
A clock gate buffering circuit is having a functional circuit without a latch that receives a clock and an enable signal. A logic voltage of an enable signal sends a corresponding clock gate signal to provide the other circuit when the clock of the functional circuit is in a rising edge. Also, the logical voltage of the enable signal sends a corresponding clock gate signal to provide the other circuit when this functional circuit is also in falling edge.
Faraday Technology Corp.
H H
H03K H03K
inventional inventional
Chih-Fu Jeng-Huang Guo-Wei
Chien Wu Li