Dentons US LLP
Systems and methods for congestion and routability aware detailed placement
Disclosed herein are systems and methods to reduce wirelength and congestion in an integrated circuit (IC) design. The systems and methods disclosed herein may be implemented during a detailed placement stage of IC design to identify and select a cell for relocation and determine an area of interest to which the cell can be relocated. The systems and methods may identify one or more potential locations within the area of interest where the cell can be relocated to, and then determine a cost based upon the wirelength and/or congestion for the selected cell, at each of the one or more potential locations. Upon determining that a potential location may have a lower cost compared to the original location of the selected cell, the systems and methods may relocate the selected cell to the potential location.
Cadence Design Systems, Inc.
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G06F Y02P G06F G06F
additional additional inventional inventional
Jhih-Rong Mehmet Charles Wen Hao Zhuo
Gao Yildiz Alpert Liu Li