Slater & Matsil, L.L.P.
Built-in bit error rate test circuit
System and method for testing jitter tolerance by using a built-in jitter modulation circuit is disclosed. An embodiment comprises a jitter modulation circuit, a transmitter, a receiver and a data comparison unit. The jitter modulation circuit includes a plurality of data latches, a phase-select block and a multi-phase clock generator. The multi-phase clock generator is capable of generating a plurality of signals having different phase shifts wherein one signal having a phase shift from the system clock signal is selected by the phase-select block. The selected signal alters the data by injecting jitter through a plurality of data latches. The jitter-contaminated data is transmitted to a data comparison unit through a transmitter and a receiver. The on-chip test circuit compares the jitter-contaminated data with the original data and calculates the bit error rate so as to determine whether the jitter tolerance of this semiconductor device satisfies the specification.
Taiwan Semiconductor Manufacturing Company, Ltd.
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inventional inventional inventional
Chih-Hsien Jinn-Yeh
Chang Chien