Placement of input-output design objects into a programmable gate array supporting multiple voltage standards
 A method and apparatus for placement into a programmable gate array of input-output (I/O) design objects having different voltage standards. The programmable gate array has a plurality of sites arranged into banks supporting interfaces with a plurality of different input and output voltage standards. In an example embodiment, I/O design objects are placed into IOBs of the programmable gate array by first performing simulated annealing that considers conflicts between design object voltage standards as placed into the IOBs. Then, a bipartite matching is performed using placement results from simulated annealing. Finally, if the bipartite matching does not produce a feasible placement, standards are assigned to the banks based on the previous placement results, and the bipartite matching process is repeated. 
Xilinx, Inc.
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G06F H03K H03K
inventional inventional inventional
Rajeev Jason H. James L. Madabhushi V. R. Sudip K.
Jayaraman Anderson Saunders Chari Nag