Schwegman Lundberg & Woessner, P.A.
Routing interconnect of integrated circuit designs with varying grid densities
Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
Cadence Design Systems, Inc.
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inventional inventional inventional
Wenyong So-Zen Limin Jing Liang-Jih
Deng Yao He Chen Chao