Sughrue Mion, PLLC
Semiconductor device having transistors formed by double patterning and manufacturing method therefor
A semiconductor device is provided which suppresses variations in transistor characteristics such as a source-drain diffusion capacitance. A first transistor TRA is formed in a first element forming area EFA as a divided transistor. A second transistor TRB is formed in a second element forming area EFB as another divided transistor. The first element forming area EFA and the second element forming area EFB are set to the same size. The first element forming area EFA and the second element forming area EFB are arranged deviated from each other in an X direction by a length SPL corresponding to the minimum pitch PT of a gate wiring GH.
Renesas Electronics Corporation
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inventional inventional inventional inventional additional
Nobuhiro Tetsuya
Tsuda Watanabe