Jaffery Watson Mendonsa & Hamilton LLP
Sparse optimizations for a matrix accelerator architecture
Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.
Intel Corporation
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Yoav Arthur Lakshminarayanan SungYe Elmoustapha Varghese Subramaniam Abhishek Ashutosh Vikranth Scott Joydeep Andrei Altug William Mike Vasanth Prasoonkumar
Harel Hunter, Jr. Striramassarma Kim Ould-Ahmed-Vall George Maiyuran Appu Garg Vemulapalli Janus Ray Valentin Koker Sadler Macpherson Ranganathan Surti