LaRiviere, Grubman & Payne, LLP
Method for fabrication of shallow isolation trenches with sloped wall profiles
 The present invention provides a method for fabricating shallow isolation trenches with sloped walls in semiconductor wafers. The method uses a conformal polysilicon layer to form an etch barrier over trench regions in a semiconductor substrate. This etch barrier has areas of varying thickness. The thickest areas of the etch barrier are located on the edges of trench structures and slow the etch process in the underlying substrate. The thinner regions of the etch barrier do not impede the etch process to as great an extent. This etch rate differential causes a sloped trench wall profile. The isolation trenches are completed by filling the surface with dielectric materials then planarizing. 
Advanced Micro Devices
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Hung-Sheng Mark S.
Chen Chang