Processor based BIST for an embedded memory
 An integrated chip having a DRAM embedded in logic is tested by an in-situ processor oriented BIST macro. The BIST is provided with two ROMS, one for storing test instructions and a second, which is scannable, that provides sequencing for the test instructions stored in the first ROM, as well as branching and looping capabilities. The BIST macro has, in addition, a redundancy allocation logic section for monitoring failures within the DRAM and for replacing failing word and/or data lines. By stacking the DRAM in 0.5 mb increments up to a 4.0 mb maximum or in 1.0 mb increments up to an 8 mb maximum, all of which are controlled and tested by the BIST macro, a customized chip design with a high level of granularity can be achieved and tailored to specific applications within a larger ASIC. 
International Business Machines Corporation
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G11C G06F G11C
inventional inventional inventional
Jeffrey Harris John Edward John Stuart Yotaro Howard Leo Donald Lawrence Rex Ngo
Dreibelbis Barth, Jr. Parenteau, Jr. Mori Kalter Wheater Kho