Method for reducing layout printability effects on semiconductor device performance
A printability simulation is performed on a mask layout over a range of lithography process conditions. A layout configuration capable of inducing functional or parametric failure in a semiconductor device is identified in the mask layout. A test structure representative of the identified layout configuration is obtained. A design of experiment is associated with the test structure. The design of experiment is defined to investigating effects of variations of one or more layout attributes in the test structure. Multiple instance of the test structure are fabricated on a wafer according to the design of experiment. Electrical performance characteristics of the fabricated test structures are measured. Based on the measured electrical performance characteristics, one or more layout attributes of the test structure capable of causing functional or parametric failure are determined.
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H01L G03F
inventional inventional
Lidia Christoph Rakesh R. Sharad
Daldoss Dolainsky Vallishayee Saxena