Interface protocol for a disk drive, SRAM and DRAM
A memory architecture for a disk drive system in which (Synchronous Random Access Memory) SRAM and Dynamic Random Access Memory (DRAM) functions are provided on separate integrated circuits, and an interface protocol for transmitting information between these two memory components are provided to improve performance of the system, as well as reduce pin count and cost. The SRAM is an “on-board” memory component, meaning that it is embodied on an integrated circuit that also includes a hard disk controller (HDC) and other disk drive components, while the DRAM is located on a separate integrated circuit externally, i.e., “off-board,” of the integrated circuit containing the SRAM. The SRAM includes a random access (RA) block that provides all RA functions, while the DRAM includes a direct memory access (DMA) block that provides all DMA functions.
Marvell International Ltd.
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Po-Chien Saeed
Chang Azimi