McDermott Will & Emery LLP
Wafer-to-design image analysis (WDIA) system
A method includes obtaining a layout of a circuit pattern implemented on a semiconductor wafer, and identifying one or more polygons in the layout based on a length criteria. One or more measurement gauges are placed on the identified polygons to thereby obtain measured polygons. A scanning electron microscope (SEM) image of the circuit pattern is obtained. The SEM image is aligned with the layout including the measured polygons. A critical dimension of one or more objects in the SEM image is measured. The one or more objects correspond to the one or more polygons. Based on the measured critical dimension, it is determined whether the circuit pattern is acceptable.
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
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Wen-Chuan Cheng-Chi
Wang Wu