Eschweiler & Associates, LLC
Capacitor array layout arrangement for high matching methodology
Some embodiments relate a capacitor array arranged on a semiconductor substrate. The capacitor array includes an array of unit capacitors arranged in a series of rows and columns. An interconnect structure couples unit capacitors of the array to establish a plurality of capacitor elements. The respective capacitor elements have different numbers of unit capacitors and different corresponding capacitances. In establishing the plurality of capacitor elements, the interconnect structure couples unit capacitors of the array in substantially identical sub-arrays tiled over the semiconductor substrate. Other methods and devices are also disclosed.
Taiwan Semiconductor Manufacturing Co., Ltd.
H G H
H01L G06F H01L
inventional inventional inventional
Chung-Ting Chih-Chiang
Lu Chang