Fish & Richardson P.C.
Semiconductor device comprising memory devices each comprising sense amplifier and memory cell
A memory device with low power consumption is provided. The memory device includes a sense amplifier, bit lines, memory cells, and first transistors. The bit lines are provided over a layer comprising the sense amplifier. The memory cells are provided over a layer comprising the bit lines. The memory cell includes a second transistor and a capacitor. The sense amplifier and the bit lines are electrically connected to each other through the first transistors. The sense amplifier may include at least one layer of a conductor.
Semiconductor Energy Laboratory Co., Ltd.
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Tatsuya Kiyoshi
Onuki Kato