Patterson & Sheridan, LLP
Multi-chip package with interconnected stacked chips
A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.
Qimonda AG
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Jong Hoon Octavian Lee Ward Oliver Wayne Frederick Josef Jung Pil Klaus
Oh Beldiman Collins Kiehl Ellis Schnell Kim Hummler