NAND Logic gate circuit having improved response time
 A NAND logic gate circuit having a first input circuit receiving a first input signal, an inverter circuit for inverting the output of the first input circuit, a second input circuit for receiving a second input signal, an AND gate circuit for producing a logical AND output signal in response to the outputs of the inverter circuit and the second input circuit, and a PNP transistor responsive to the second input signal having a low value for controlling the value of the output signal of the first input circuit independent of the value of the first input signal. The NAND gate circuit has a faster response time to changes in the value of the first input signal than comparable prior art circuits and reduces the current flow to the second input terminal when the first input signal is high and the second input signal is low. 
Nippon Electric Co., Ltd.
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inventional inventional inventional
Susumu Hideaki
Mori Yamada