Duane Morris LLP
Phase-locked loop monitor circuit
A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
Taiwan Semiconductor Manufacturing Co., Ltd.
H H H H
H03K H03L H03L H03L
additional inventional inventional inventional
Ji-Jan Yun-Han Stanley Sandeep Kumar Yen-Hao
Chen Lee John Goel Huang