Haynes and Boone, LLP
Method and apparatus for achieving multiple patterning technology compliant design layout
A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved. If the pattern layout is a multiple patterning compliant layout, the method includes coloring each of the plurality of features based on the color of each feature's corresponding at least one routing track, thereby forming a colored pattern layout, and generating at least two masks with the features of the colored pattern layout. Each mask includes features of a single color.
Taiwan Semiconductor Manufacturing Company, Ltd.
G G G
G03F G06F G03F
inventional inventional inventional
Li-Chun Huang-Yu Wen-Chun Ken-Hsien Fang-Yu Ru-Gun Lee Fung Lee-Chung Yuan-Te
Tien Chen Huang Hsieh Fan Liu Song Lu Hou