Dicke, Billig & Czaja, PLLC
DQS for data from a memory array
A memory comprises a first circuit, a second circuit, and a latch. The first circuit is configured to provide a first signal indicating an earliest time valid data is available from a memory array in response to a read command. The second circuit is configured to provide a second signal indicating a latest time valid data is available from the memory array in response to the read command. The latch is configured to be connected to a data line coupled to the memory array in response to the first signal and disconnected from the data line in response to the second signal to latch data read from the memory array.
Infineon Technologies AG
G G G G
G11C G11C G11C G11C
inventional inventional inventional inventional
Jung Pill Alessandro
Kim Minzoni