Pillsbury Winthrop Shaw Pittman, LLP
Decoder and decoding method for decoding irregular low-density parity-check codes
In one embodiment, bit processing units are provided for the 1st to Mth rows (M=p1×m1) of a parity-check matrix that includes a first parity-check matrix and second parity-check matrix adjacent thereto. The first and second parity-check matrices include (n1×m1) and (n2×m2) permuted matrices, respectively. The bit processing units sequentially update bit information corresponding to column positions included in the respective rows of the first and second parity-check matrices, a bit at each of the column positions being set to “1”. Parity processing units update parity information corresponding to row positions in p1 columns of each of the n1 column blocks of the first parity-check matrix, and corresponding to row positions in p2 columns of each of the n2 column blocks of the second parity-check matrix, a bit at each of the row positions being set to “1”.
Kabushiki Kaisha Toshiba
H H H
H03M H03M H03M
inventional inventional inventional
Kenji
Yoshida