Myers Bigel Sibley & Sajovec, PA
Methods of fabricating semiconductor devices having a dual stress liner
In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.
Samsung Electronics Co., Ltd. Chartered Semiconductor Manufacturing, Ltd.
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Young Way Jae-Eon Dae-Kwon Jun-Jung Ja-Hum
Teh Park Kang Kim Ku