Stites & Harbison PLLC
Transmitter and receiver using forward clock overlaying link information
A transmitting and receiving technique in which a load on data signal lines is reduced while maintaining a communication quality, thereby making it possible to improve the throughput of data channels. In a transceiver, a transmitter side has an encoder circuit that transmits a bit sequence obtained by encoding link information to a clock signal line, and a receiver side has a clock and data recovery circuit 17 that extracts a clock component from a signal received from the clock signal line, a decoder circuit 19 that decodes the extracted signal to reproduce the link information, and a bit deskew circuit 21 that adjusts a skew that is lower than one bit on the basis of a clock component.
Hitachi, Ltd.
H
H04L
inventional
Tatsuya Hiroki Hidehiro Norio
Saito Yamashita Toyoda Chujo