Prevention of die loss to chemical mechanical polishing
Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modern high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.
Taiwan Semiconductor Manufacturing Company
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Chung-Long Syun-Ming Chen-Hua Tsu Jeng-Horng Jui-Yu
Chang Jang Yu Shih Chen Chang