Tutunjian & Bitetto, P.C.
Vertical fin field effect transistor device with reduced gate variation and reduced capacitance
A method of forming a fin field effect transistor device is provided. The method includes forming a vertical fin on a substrate, and depositing a sidewall liner on exposed surfaces of the vertical fin. The method further includes removing a portion of the substrate below the sidewall liner to form a support pillar below the vertical fin. The method further includes laterally etching the support pillar to form a thinned support pillar, and forming a bottom source/drain layer on the substrate and the thinned support pillar, wherein the bottom source/drain layer has a non-uniform thickness.
INTERNATIONAL BUSINESS MACHINES CORPORATION
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Shogo Juntao Kangguo Choonghyun
Mochizuki Li Cheng Lee