Haynes and Boone, LLP
Method of fabricating an integrated circuit with a pattern density-outlier-treatment for optimized pattern density uniformity
The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.
Taiwan Semiconductor Manufacturing Company, Ltd.
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inventional additional additional inventional
Shy-Jay Jyuh-Fuh Pei-Yi Wen-Chuan Cheng-Hung Burn Jeng
Lin Lin Liu Wang Chen Lin