Huse IP Law
Defect-location determination using correction loop for pixel alignment
A method of semiconductor-wafer image alignment is performed at a semiconductor-wafer defect-inspection system. In the method, a semiconductor wafer is loaded into the semiconductor-wafer defect-inspection system. Pre-inspection alignment is performed for the semiconductor wafer. After performing the pre-inspection alignment, a first swath is executed to generate a first image of a first region on the semiconductor wafer. An offset of a target structure in the first image with respect to a known point is determined. Defect identification is performed for the first image, using the offset. After executing the first swath and determining the offset, a second swath is executed to generate a second image of a second region on the semiconductor wafer. While executing the second swath, run-time alignment of the semiconductor wafer is performed using the offset.
KLA Corporation
G G H G
G06T G06T H01L G06T
inventional additional inventional additional
Xiaochun Bjorn Santosh Hucheng Tarunark David Sangbong Bryant
Li Brauer Bhattacharyya Lee Singh Dowling Park Mantiply