Test method for a semiconductor memory device applied to a margin test
 There is provided a test method for a semiconductor memory device which can be applied to a margin test, for example. The memory device has two types of sense amplifiers each composed of a layout pattern symmetrical to the other and arrayed such that the layout patterns alternate, memory cells, bit lines which are connected to the sense amplifiers and which carry signals expressing data stored in the memory cells, work lines, gates connected to bit lines, and a comparator which receives signals on bit lines via the gates and determines whether or not the signals match. The test method has a step which stores identical data in the memory cells connected by the bit lines to the two types of sense amplifiers; a step which raises the level of word line, communicating the memory cell to the bit line to receive a signal expressing the stored data from the memory cell on the bit line, and amplifying by means of the sense amplifier the signal expressing the stored data; and a step which communicates the bit lines connected to differing types of sense amplifiers to the comparator by turning the gates ON, and compares the signals on the bit lines amplified by differing types of sense amplifiers to detect data errors or data not matching. 
Sharp Kabushiki Kaisha
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inventional inventional inventional additional
Masaru
Nawaki