Hoffman Warnick LLC
Integrated circuit structure having substantially planar N-P step height and methods of forming
Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.
International Business Machines Corporation GLOBALFOUNDRIES Inc.
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inventional inventional inventional
Deleep R. Young Way Weipeng Voon-Yew Jae-Eun
Nair Teh Li Thean Park