Jianq Chyun IP Office
Slew rate control circuit and method thereof and slew rate control device
A slew rate control circuit is provided. The slew rate control circuit includes at least one switch and an inverter. A first end of the switch is coupled to a power terminal. A toggle end of the switch is coupled to a first control terminal. A second end of the switch is coupled to an output terminal. An output end of the inverter is coupled to the output terminal. An input end of the inverter is coupled to an input terminal. A voltage at the first control terminal conducts the switch to reduce the slew rate when a large voltage variation occurs at the output terminal. A method of controlling a slew rate and a slew rate control device are provided.
Elite Semiconductor Memory Technology Inc.
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inventional inventional inventional inventional
Chin-Yang Jian-Wen
Chen Chen