Kenyon & Kenyon LLP
Power domain crossing interface analysis
A method is provided to test an integrated circuit design for power management circuit design errors comprising: configuring a computer to identify multiple power domain crossing paths between pairs of power domains; identify one or more power related constraints associated with such power domain crossing paths; and group power domain crossing paths between matching power domain pairs that are associated with matching power related constraints.
Cadence Design Systems, Inc.
G G
G06F G06F
additional inventional
Mitchell W Reuber Chung-Fu
Hines Duarte Chang