Method of planarization using dummy leads
 An Integrated Circuit Design which adds, to the standard conducting lines of the bulk metal layer, a pattern of a support structure which supports subsequent deposition in such a way that it eliminates previously experienced concavity or dishing of the subsequent deposition within areas which have a low density or absence of conducting lines. The dummy pattern enhances the deposition of filler material between conducting lines of the Integrated Circuit such that planarization of the bulk metal results in a smoother surface of the areas of the signal lines of the integrated circuit and within large open areas. Concurrently the present invention provides a means of successfully collecting data that are needed for Damascene processing. 
Taiwan Semiconductor Manufacturing Company
H H
H01L H01L
inventional inventional
Jing-Meng Chia-Shiung Tsu Chi-Wen
Liu Tsai Shih Liu