Conley, Rose & Tayon, PC
Microprocessor configured to detect memory operations having data addresses indicative of a boundary between instructions sets
 A microprocessor configured to detect a memory operation having a predefined data address is provided. The predefined data address indicates that subsequent instructions belong to an alternate instruction set. In one embodiment, a second memory operation having the predefined data address indicates that instructions subsequent to the second memory operation belong to the original instruction set. The memory operations effectively provide a boundary between the instructions from dissimilar instruction sets. Instructions are routed to an execution unit configured to execute the instruction set indicated by the most recently detected memory operation having the predefined address. Each instruction sequence within the program may be coded using the instruction set which most efficiently executes the function corresponding to the instruction sequence. The program may be executed more quickly than an equivalent program coded entirely in either instruction set. In one embodiment, the microprocessor executes the x86 instruction set and the ADSP 2171 instruction set. 
Advanced Micro Devices, Inc.
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inventional inventional inventional inventional
John G. Thang M.
Bartkowiak Tran