Haynes and Boone, LLP
Integrated circuit layout design
Provided is a method including layout design of an integrated circuit. A first pattern is provided. The first pattern includes an array of dummy line features and a plurality of spacer elements abutting the dummy line features. A second pattern is provided. The second pattern defines an active region of an integrated circuit device. An edge spacer element of the active region is determined. A dummy line feature of the array of dummy line features is biased (e.g., increased in width), the dummy line feature is adjacent an edge spacer element.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Shinn-Sheng Ming-Feng Anthony Jeff J. Chang-Yun Clement Hsingjen Shao-Ming
Yu Shieh Yen Xu Chang Wann Yu