Merchant & Gould P.C.
Memory device
A memory device is provided. The memory device includes a shift register array having a plurality of shift registers arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of rows comprises a first plurality of shift registers and each of the plurality of columns comprises a second plurality of shift registers. Each of the plurality of rows are associated with a read word line and a write word lines. Each of the plurality of rows are associated with a data input line and a data output line. Each of the plurality of shift arrays comprises a static random access memory.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
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Yen-Huei Hiroki Wei-Chang Chih-Yu Hidehiro Hsien-Yu
Chen Noguchi Zhao Lin Fujiwara Pan