Eschweiler & Potashnik, LLC
Contact field plate
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a gate structure disposed over a substrate between a source region and a drain region. A first inter-level dielectric (ILD) layer is disposed over the substrate and the gate structure and a second ILD layer is disposed over the first ILD layer. A field plate etch stop structure is between the first ILD layer and the second ILD layer. A field plate extends from an uppermost surface of the second ILD layer to the field plate etch stop structure. A plurality of conductive contacts extend from the uppermost surface of the second ILD layer to the source region and the drain region.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Jyun-Guan Chia-Cheng Yu-Chang Hui-Ting Pei-Lun
Jhou Ho Jong Lu Wang