Patterson & Sheridan, L.L.P.
Compute-in-memory (CIM) binary multiplier
Certain aspects provide methods and apparatus for binary computation. An example circuit for such computation generally includes a memory cell having at least one of a bit-line or a complementary bit-line; a computation circuit coupled to a computation input node of the circuit and the bit-line or the complementary bit-line; and an adder coupled to the computation circuit, wherein the computation circuit comprises a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell, and a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, drains of the first NMOS and PMOS transistors being coupled to the adder, wherein a source of the first PMOS transistor is coupled to a reference potential node, and wherein a source of the first NMOS transistor is coupled to the computation input node.
QUALCOMM Incorporated
G H G G G G
G06N H04N G06N G06N G06F G06F
inventional inventional inventional additional inventional inventional
Periannan Xia Zhongze
Chidambaram Li Wang