Eschweiler & Associates, LLC
SiGe based gate driven PMOS trigger circuit
Some embodiments of the present disclosure relate to a low-power, area efficient ESD protection device that provides ESD protection to an ESD susceptible circuit. The ESD protection device has a trigger circuit with a resistor. The resistor has a first terminal connected to the first external pin and a second terminal connected directly to a gate of a SiGe based PMOS shunt transistor. The trigger circuit generates a trigger signal that drives the gate of the PMOS device to shunt power away from the ESD susceptible circuit when an ESD event is present. The SiGe based PMOS shunt transistor has a lower gate leakage than a conventional NMOS shunt transistors, thereby providing for an ESD circuit with a low leakage current at small gate lengths.
Taiwan Semiconductor Manufacturing Co., Ltd.
Y H
Y10T H02H
additional inventional
Kuo-Ji Wen-Han
Chen Wang