WPAT, P.C., Intellectual Property Attorneys
Semiconductor structure and manufacturing method of the same
The present disclosure provides a semiconductor package, including a semiconductor die and a substrate having a first surface electrically coupled to the semiconductor die and a second surface opposing to the first surface. The first surface includes a core region having a plurality of landing pads and a periphery region surrounding the core region and having a plurality of landing traces. A pitch of the landing pads is from about 55 μm to about 280 μm. The semiconductor die includes a third surface facing the first surface of the substrate and a fourth surface opposing to the third surface. The third surface includes a plurality of elongated bump positioned correspondingly to the landing pads and the landing traces of the substrate, and the elongated bump includes a long axis and a short axis perpendicular to the long axis on a cross section thereof.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
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additional inventional additional additional additional additional additional inventional additional additional inventional additional additional additional inventional additional additional additional inventional additional additional additional additional additional inventional inventional
Yu-Feng Tin-Hao Chen-Shien Mirng-Ji Sheng-Yu Yen-Liang
Chen Kuo Chen Lii Wu Lin