Processor micro-architecture for compute, save or restore multiple registers and responsive to first instruction for repeated issue of second instruction
An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of said bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue said second instruction with said operand varied in an operand value range determined as a function of the varying bias value.
Texas Instruments Incorporated
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Hiroyuki Kenichi Yuji
Mizuno Tashiro Umemoto