Reset signal generation circuit having a function for protecting write data
 In a reset signal generation circuit for generating a reset signal to a CPU in accordance with an external clock signal, illegal operation or loss of write data during a write period is prevented. A means (14) is provided for prohibiting the generation, in accordance with an external reset signal (RST), of a reset signal (RESET) to the CPU during a data write period of the CPU, and, according to a preferred embodiment of the invention, a means is provided for holding the external reset signal until a reset signal is generated to the CPU. 
Motorola, Inc.
G
G06F
inventional
Hidekazu
Ito