Oblon, Spivak, McClelland, Maier & Neustadt
Semiconductor memory device
 A semiconductor memory device comprises a memory array including a plurality of memory cells arranged in a matrix form, a plurality of word lines arranged in column and a plurality of bit lines arranged in row. Each memory cell includes a bipolar transistor in which a collector-emitter voltage is controlled so that the polarity of a base current changes is changed in accordance with an increase in a base-emitter voltage, and a switching element, provided between the base of the bipolar transistor and an associated bit line and controllable by an associated word line. A switch circuit is provided for applying a collector voltage to the collector of the bipolar transistor smaller in a second state where an associated one of the memory cells is holding data than in a second state where the associated memory cell is accessible for data reading and data writing. 
Kabushiki Kaisha Toshiba
G G G
G11C G11C G11C
inventional inventional inventional
Takehiro Koji Shigeyoshi Fujio
Hasegawa Sakui Watanabe Masuoka