Jianq Chyun IP Office
Multi-level non-volatile memory
A multi-level non-volatile memory including a memory cell disposed on a substrate is provided. The memory cell includes a control gate, a charge storage layer, a doped region, a select gate, and an assist gate. The control gate is disposed on the substrate. The charge storage layer is disposed between the control gate and the substrate. The doped region is disposed in the substrate at the first side of the control gate. The select gate is disposed on the sidewall of the first side of the control gate and on the substrate between the control gate and the doped region. The assist gate is disposed on the sidewall of the second side of the control gate. An inversion layer is formed in the substrate below the assist gate when a voltage is applied to the assist gate.
Powerchip Semiconductor Corp.
H H G H H
H01L H01L G11C H01L H01L
inventional inventional inventional inventional inventional
Chih-Chen Chih-Wei
Chou Hung