Sughrue, Mion, Zinn, Macpeak & Seas, PLLC
Semiconductor memory having signal input circuit of synchronous type
 External control signals are input to a semiconductor memory device via a synchronizing semiconductor circuit. An internal clock (ICLK) in the synchronizing semiconductor circuit is produced as a phase shifted version of an external clock (S11) which is input to the memory device. First latch circuits (321-324) latch external control signals in response to the external clock (S11). Decoder circuits (331.sub.0 -331.sub.n) produce internal control signals (S31.sub.0 -S331.sub.n) based upon the latched signals (S21-S24) output from the first latch circuits (321-324). Second latch circuits (341.sub.0 -341.sub.n) latch the internal control signals (S31.sub.0 14 S31.sub.n) in response to the internal clock signal (ICLK). 
NEC Corporation
G
G11C
inventional
Mamoru
Fujita