Jones & Volentine, L.L.P.
Multichip package device having a lead frame with stacked patterned metallization layers and insulation layers
 A multichip package device includes a lead frame having supporting portions and lead portions for electrically connecting the multichip package with an external electronic device. The multichip package is formed by depositing first and second inner insulation layers on lower and upper surfaces of the lead frame, respectively. Via holes are then formed through the first and the second inner insulation layers. First and second metallization layers are deposited and patterned on lower and upper surfaces of the first and the second inner insulation layers, respectively. First and second outer insulation layers are then deposited on lower and upper surfaces of the first and the second patterned metallization layers, respectively. A plurality of chips, each having an active surface on which a plurality of bonding pads are formed, are attached to lower and upper surfaces of the first and second outer insulation layers. A plurality of bonding wires are connected between the plurality of bonding pads and the lead portions through the via holes and the first and second patterned metallization layers. 
Samsung Electronics Co., Ltd.
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Jeong Woo
Seo