Staas & Halsey
Semiconductor memory device that uses a negative differential resistance
 A semiconductor memory device comprises a memory cell transistor that includes two active parts each including therein an emitter and a base and showing a negative differential resistance. The collector layer is shared commonly by the two active parts and is connected to a bit line, while the emitters forming the two active parts are connected to respective word lines that form a word line pair. The bit line and the word lines forming the word line pair are biased to realize a bistable operational state in the memory cell transistor to hold the information. 
Fujitsu Limited
H G
H01L G11C
inventional inventional
Naoki Toshihiko
Yokoyama Mori