McClure, Qualey & Rodack, LLP
Method for operating memory array
A method for operating a memory array is disclosed. The memory array includes a first memory cell, a second memory cell and a third memory cell sharing a gate and arranged along an extending direction of the gate in order. The method includes the following steps. A first bias is applied to a channel of the first memory cell to program the first memory cell. A second bias is applied to a channel of the second memory cell to inhibit programming of the second memory cell. A third bias is applied to a channel of the third memory cell to program or inhibit programming of the third memory cell. The first bias and the third bias are different.
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Yao-Wen Yung-Hsiang I-Chen
Chang Chen Yang