Schwabe, Williamson & Wyatt, P.C.
CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
Intel Corporation
H H H H B H H H H H H H H H H H H H H H H H H H
H01L H01L H01L H01L B82Y H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L
inventional additional inventional additional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional additional inventional inventional inventional additional inventional inventional inventional inventional inventional
Matthew Benjamin Jack Robert Marko Gilbert Willy Van Niloy Ravi
Metz Chu-Kung Kavalieros Chau Radosavljevic Dewey Rachmady Le Mukherjee Pillarisetty