Haynes and Boone, LLP
Method for integrated circuit manufacturing
Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
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Ming-Hsuan Chun-Hung Cheng Kun Ching-Hsu Ping-Chieh Ru-Gun Feng-Ju Wen-Chun Wen-Hao Feng-Lung Hung-Chun
Wu Wu Tsai Chang Wu Liu Chang Huang Liu Lin Wang