Blakely, Sokoloff, Taylor & Zafman
Method of fabricating MOS transistor having shallow source/drain junction regions
A method of fabricating a MOS transistor having shallow source/drain junction regions is provided. A diffusion source layer is formed on a semiconductor substrate on which gate patterns are formed. Same type or different type of impurities are implanted into the diffusion source layer several times in different directions. As a result, dislocation does not occur and the impurity concentration of the diffusion source layer can be nonuniformly controlled so that damage to the crystal structure of the semiconductor substrate does not occur. Also, the impurities nonuniformly contained in the diffusion source layer are diffused into the semiconductor substrate by a solid phase diffusion method to form shallow source/drain junction regions having LDD regions and highly doped source/drain regions by a self-alignment method.
Electronics and Telecommunications Research Institute
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inventional additional inventional inventional inventional
Seong-jae Won-ju Kyoung-wan
Lee Cho Park