Oliff & Berridge, PLC
Method of manufacturing layered chip package
A layered chip package includes a main body, and wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of semiconductor chips stacked, and a plurality of electrodes that electrically connect the semiconductor chips to the wires. A method of manufacturing the layered chip package includes the steps of: fabricating a substructure that includes an array of a plurality of pre-separation main bodies and a plurality of holes for accommodating a plurality of preliminary wires, the holes being formed between two adjacent pre-separation main bodies; forming the preliminary wires in the plurality of holes by plating; and cutting the substructure so that the plurality of pre-separation main bodies are separated from each other and the preliminary wires are split into two sets of wires of two separate main bodies, whereby a plurality of layered chip packages are formed.
Headway Technologies, Inc. SAE Magnetics (H.K.) Ltd.
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Atsushi Yoshitaka Hiroyuki
Iijima Sasaki Ito