Myers Bigel Sibley & Sajovec
Isolation layers for semiconductor devices including first and second sub-trenches and methods of forming the same
In a device isolation layer for a p-MOS transistor and a method of forming the same, a trench oxide layer having a first and a second sub-oxide layers is formed in a trench including a first and a second sub-trenches. The first and second sub-oxide layers are formed on side and bottom surfaces of the first and second sub-trenches, respectively. The second sub-trench has a width greater than the first sub-trench. The first sub-oxide layer has a first thickness that is uniform along the side and bottom surfaces of the first sub-trench and the second sub-oxide layer has a second thickness greater than the first thickness along the side surface of the second sub-trench. A liner layer is formed on the trench oxide layer, and an insulation pattern is formed on the liner layer.
Samsung Electronics Co., Ltd.
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inventional inventional additional inventional
Yun-Sung
Lee