IP & T Group LLP
Memory device and method of operating the same
The present disclosure relates to a memory device includes a memory cell array, a peripheral circuit and a program operation controller. The memory cell array including a plurality of memory cells each having a target programmed state among a plurality of programmed states. The peripheral circuit performs at least one program loop including applying a program voltage to a word line coupled in common to the plurality of memory cells, and selectively performing a verify operation of determining whether a threshold voltage of each of the plurality of memory cells exceeds a verify voltage. The program operation controller controls the peripheral circuit to perform the at least one program loop corresponding to at least one of remaining programmed states other than a most significant programmed state among the plurality of programmed states, and apply a program pulse corresponding to the most significant programmed state to the word line.
SK hynix Inc.
G G G G G G G G
G11C G11C G11C G11C G11C G11C G11C G11C
inventional additional inventional inventional inventional inventional inventional inventional
Hyung Jin
Choi