William Park & Associates Ltd.
Test modes for a semiconductor memory device with stacked memory chips using a chip identification
A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device controls a test mode. The first semiconductor device outputs a chip identification and receives external data. The second semiconductor device includes a plurality of memory chips. At least one of the plurality of memory chips are activated based on the chip identification to store input data into each of the plurality of memory chips that have been activated while a write operation is performed in the test mode. At least two of the plurality of memory chips are activated based on the chip identification to output the stored input data as the external data while a read operation is performed in the test mode.
SK hynix Inc.
H G G H H H H G G H H H G H H
H01L G11C G11C H01L H01L H01L H01L G11C G11C H01L H01L H01L G11C H01L H01L
additional inventional inventional additional additional additional additional inventional inventional additional additional additional inventional additional additional
Seong Ju
Lee