Paradice and Li LLP
CMOS analog circuits having a triode-based active load
A continuous time linear equalizer (CTLE) is disclosed. The CTLE may include a first cell configured to buffer and invert an input signal and generate a first intermediate signal, a second cell configured to buffer and invert the input signal and generate a second intermediate signal, and a first frequency section configured to selectively buffer and invert a first range of frequencies of the second intermediate signal. The first frequency section may include a first tunable resistor configured to provide a first resistance and a third cell coupled to the first tunable resistor configured to generate a third intermediate signal based on the first resistance.
Xilinx, Inc.
H H H H
H04L H04L H01L H04L
inventional inventional inventional inventional
Hsung Jai Kevin Chuen-Huei
Im Zheng Chou