Alston & Bird LLP
Clock and data recovery circuits
A data communication system comprising a first transmitter set configured to transmit a first output based on a first signal, the first output including one of a training pattern and a first data, the training pattern and the first data including clock information, a second transmitter set configured to transmit a second output based on the first signal, the second output including one of the training pattern and a second data, a first receiver set configured to generate a first received data based on the first output, a second receiver set configured to generate a second received data based on the second output, a clock and data recovery (CDR) circuit configured to extract the clock information based on the first signal and the first received data and provide a second signal indicating whether a frequency in-lock status is reached, a phase control circuit in the second receiver set, the phase control circuit being configured to detect a phase difference between the first received data and the second received data and provide a third signal indicating whether a phase in-lock status is reached, and a detector configured to generate the first signal based on the second signal and the third signal.
Trendchip Technologies, Corp.
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Hsin-Hsien Yung-Tai
Li Chen