Locke Lord LLP
Display panel
A display panel includes a signal generating circuit, a pixel array disposed adjacent to the signal generating circuit, and a plurality of gate driver circuits disposed adjacent to the signal generating circuit and the pixel array. The signal generating circuit is configured to provide a plurality of clock signals and a plurality of data signals. The gate driver circuits are configured to convert the clock signals to a plurality of gate signals and transfer the gate signals to the pixel array. The pixel array is configured to receive the gate signals and the data signals for display. Delays of the gate signals increase along a first direction, delays of the data signals increase along a second direction, and the second direction is opposite to the first direction. The signal generating circuit is further configured to calibrate the gate signals and the data signals.
AU OPTRONICS CORPORATION
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Mei-Yi Shiang-Lin Yu-Chieh
Li Lian Kuo