Increased surface area for DRAM, storage node capacitors, using a novel polysilicon deposition and anneal process
 A process for fabricating a stacked capacitor, DRAM, device, with an optimized lower electrode structure, has been developed. The surface area of the lower electrode has been increased by using a specific polysilicon deposition process, featuring the use of Si2H6, followed by specific insitu anneals, initially in nitrogen, and then in a vacuum. 
Industrial Technology Research Institute
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H01L Y10S
inventional additional
Chine-Gie Yu-Hua
Lou Lee