Slater & Matsil, L.L.P.
Flip-flop circuit design
A flip-flop circuit includes a precharge circuit that outputs a charge signal high when a received clock signal is LOW. A delay clock input circuit generates a delayed clock input controlled signal with the same value as an input signal when the clock signal is HIGH. A charge keeper circuit, upon receiving the charge signal and the delayed clock input controlled signal, generates a charge keeping signal, which equals the charged signal when the clock signal is LOW and equals the delayed clock input controlled signal when the clock signal is HIGH. A separator circuit can receive the charge keeping signal and clock signal and generate an inverted charge keeping signal. A storage circuit is configured to receive the inverted charge keeping signal, a present state signal, and inverted present state signal, and to generate a present state signal and an inverted present state signal.
Taiwan Semiconductor Manufacturing Company, Ltd.
H
H03K
inventional
Yi-Tzu Chung-Cheng Chi-Lin
Chen Chou Liu