Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells
A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of chamfer shorts, and the second DOE contains fill cells configured to enable NC detection of corner shorts. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.
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Nobuharu Sheng-Che Hans Vyacheslav Hideki Carl Jeremy Kimon Christopher Simone Tomasz Rakesh Sherry Kelvin John Indranil Timothy Marci Dennis Larg Stephen Jonathan Conor Markus Marcin Andrzej
Yokoyama Lin Eisenmann Rovner Matsuhashi Taylor Cheng Michaels Hess Comensoli Brozek Vallishayee Lee Doong Kibarian De Fiscus Liao Ciplickas Weiland Lam Haigh O'Sullivan Rauscher Strojwas Strojwas