Renaissance IP Law Group LLP
Semiconductor device having pinned layer with enhanced thermal endurance
A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.
SAMSUNG ELECTRONICS CO., LTD.
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Ki-Woong Hee-Ju Yun-Jae Jae-Hoon Jeong-Heon Se-Chung Woo-Jin Joon-Myoung
Kim Shin Lee Kim Park Oh Kim Lee