Locke Lord LLP
Clock deadlock detecting system, method, and non-transitory computer readable storage medium
A clock deadlock detecting system includes a memory and a processor. The memory is configured to store at least one computer program. The processor is configured to execute the at least one computer program to perform following operations: extracting hierarchy information of a plurality of integrated clock gating (ICG) cells, in which the hierarchy information is a description of a circuit structure of the ICG cells; generating at least one checking property according to integrated circuit design information and the hierarchy information; determining whether the ICG cells satisfy the at least one checking property according to the integrated circuit design information and a formal method to determine whether the ICG cells is expected to fall into at least one clock deadlock state, so as to generate a determination result; and modifying the integrated circuit design information according to the determination result.
REALTEK SEMICONDUCTOR CORPORATION
G H G G G G G G
G06F H03L G06F G06F G06F G06F G06F G06F
inventional inventional additional inventional additional inventional additional additional
Yu-Lan Shu-Yi I-Hsiu Yung-Jen
Lo Kao Lo Chen