Thelen Reid & Priest LLP
Synchronous memory device having a plurality of clock input buffers
 A synchronous memory device having a plurality of clock input buffers includes a first clock input buffer for generating an enable signal of a data output buffer, and a second clock input buffer for generating a signal to latch external input signals (i.e., an address signal, a row address strobe (RAS) signal, a column address strobe (CAS) signal and so on). As a result, the synchronous memory device achieves a clock access time of a high speed, and reduces a current consumption in a standby mode. 
Hyundai Electronics Industries Co., Ltd.
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G11C G11C
inventional inventional
Jung Pill
Kim