Marger, Johnson, & McCollom, P.C.
Syntax parser for a MPEG2 video decoder
 Disclosed is a syntax parser for a video decoder for MPEG2 and includes: a shift register which executes the shift operation after receiving MPEG video bitstream; a ROM which stores a program decoding variable length and controlling the hardware operation, and outputs the micro-instruction according to an address; a counter which controls the address of the ROM; a register which stores parameters for decoding MPEG video; a flag controller which generates the flag from a particular code included in the bitstream or the combination of parameters, and outputs the flag; a memory which stores the table related to variable length decoding; and a length controller which gets length information to be shifted from the memory, the micro-instruction or the output of the register. The syntax parser for a MPEG2 video decoder can execute VLD and parse the MPEG bitstream. Using micro-instructions to perform the parsing function decreases the decoding time for the bitstream and obtains the parsing speed corresponding to the MP@HL of the HDTV (high definition television) standard. 
Samsung Electronics, Co., Ltd.
G
G06T
inventional
Seong-Won
Lee