Duane Morris LLP
Multi-phase clock generator
A clock generator includes a first latch configured to output a first intermediate clock phase signal based on a first clock signal and a second intermediate clock phase signal. A first phase interpolation circuit has a first input coupled to a first input of the first latch and a second input coupled to a first output of the first latch. The first phase interpolation circuit is configured to output a first clock phase signal based on the first and second intermediate clock phase signals.
Initio Corporation
H H
H03K H03K
inventional additional
Wei Zhenchang Haiming
Wang Du Tang