Finnegan, Henderson, Farabow, Garrett and Dunner
Extreme level circuit
 An extreme level circuit for detecting an extreme level of two input signals. The circuit includes a differential circuit wherein a pair of differential transistors are connected their emitters with each other and a common current source is connected to the emitter junction node of the differential transistors, a pair of emitter follower transistors coupled to the differential circuit for applying the input signals to the bases of the differential transistors and a pair of bias generating circuits each coupled in series with one of the emitter follower circuits, wherein each bias generating circuit has a bias transistor whose base is connected to a fixed bias source and a current source connected in series with the bias transistor, and wherein the pair of bias generating circuits are cross connected to the collectors of the differential transistors. 
Kabushiki Kaisha Toshiba
G
G01R
inventional
Toshikazu
Fujii