Eschweiler & Associates, LLC
PVT-free calibration circuit for TDC resolution in ADPLL
The present disclosure relates to an all digital phase locked loop (APDLL) that can account for variations in PVT conditions, and a related method of formation. In some embodiments, the ADPLL has a controllable time-to-digital converter (TDC) having a plurality of variable delay elements. The controllable TDC is determines a phase difference between a frequency reference signal and a local oscillator clock signal and to generate a phase error therefrom. A digitally controlled oscillator (DCO) varies a phase of the local oscillator clock signal based upon the phase error. A calibration unit determines an effect of variations in PVT (process, voltage, and temperature) conditions based upon the phase error and to generate a TDC tuning word that adjusts a delay introduced by one or more of the plurality of variable delay elements to account for the variations in PVT conditions.
Taiwan Semiconductor Manufacturing Co., Ltd.
H H H H
H03L H03L H03L H03L
inventional inventional additional inventional
Hsien-Yuan Huan-Neng Robert Bogdan Lee Tsung Feng Wei Kuang-Kai Chewn-Pu
Liao Chen Staszewski Hsiung Kuo Yen Jou