Qualcomm Incorporated
Integrated device comprising memory bitcells comprising shared preload line and shared activation line
A memory circuit that includes a memory bitcell. The memory bitcell includes a six-transistor circuit configuration, a first transistor coupled to the six-transistor circuit configuration, a second transistor coupled to the first transistor, a third transistor coupled to the second transistor, and a capacitor coupled to the second transistor and the third transistor. The memory circuit includes a read word line coupled to the third transistor, a read bit line coupled to the third transistor, and an activation line coupled to the second transistor. The memory bitcell may be configured to operate as a NAND memory bitcell. The memory bitcell may be configured to operate as a NOR memory bitcell.
QUALCOMM Incorporated
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Xia Xiaonan Xiaochun Yandong Ye Zhongze
Li Chen Zhu Gao Lu Wang