Christopher P. Maiorana, PC
High speed FIFO synchronous programmable full and empty flag generation
An apparatus comprising a flag generation circuit configured to generate a full flag signal in response to (i) a read clock signal, (ii) a write clock signal and (iii) a look ahead bitwise comparison configured to detect when a read count signal and a write count signal are equal.
Cypress Semiconductor Corp.
G G
G06F G06F
inventional additional
Parinda Johnie Chia Jen
Mekara Au Chang