McDermott, Will & Emery
Semiconductor device having a monitor pattern
Lead interconnection layers and are electrically connected to the respective source and drain regions of a pair of a monitor transistor MT. Lead interconnection layers and are both formed on same insulating layer and on same insulating layer as is a bit line conductive layer of a memory cell area. Furthermore, lead interconnection layers and have respective contact sections each with a large width and to each of which a needle of a probe can be connected externally. With such a structure adopted, there can be obtained a semiconductor device capable of monitoring a transistor characteristic correctly and easily by reducing parasitic resistance, further, at an early stage in a wafer process; and a fabrication process therefor.
Renesas Technology Corp.
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inventional additional inventional additional
Masahiko
Takeuchi