Rader, Fishman & Grauer
Serial to parallel conversion apparatus with means to adjust the phase of a plurality of divided clock signals
 The invention provides a serial to parallel conversion apparatus which can perform desired serial to parallel conversion processing at a high speed while it has a simple and small-scale circuit configuration. The serial to parallel conversion apparatus includes a first divider for dividing a first clock signal into 2 to produce a second clock signal and adjusting the phase of the second signal in accordance with a first phase adjustment signal, a first serial to parallel converter for converting serial data into parallel data of 2 bits in response to the second clock signal, a pair of shift registers for receiving and storing the different bits of the parallel data and successively shifting the stored bits in response to the second clock signal, a second divider for dividing the second clock signal into 4 to produce a third clock signal, a second detector for producing the first phase adjustment signal and the second phase adjustment signal based on the stored data of the shift registers, and a pair of second serial to parallel converters for receiving the different bits of the parallel data and each producing first parallel data of 4 bits in response to the third clock signal. 
Sony Corporation
H
H03M
inventional
Tohru Hidekazu
Takeshita Kikuchi