Method and apparatus to generate clock and control signals for over-clocking recovery in a PLL
An apparatus comprising a circuit that may be configured to (i) change a frequency of one or more first signals in response to a second signal and (ii) generate a third signal in response to either the second signal or a predetermined time period expiring.
Cypress Semiconductor Corp.
G
G06F
inventional
Paul Lap Tak Kuang-Yu Hyunbae Frank Hueng-Cheng Eric
Cheng Chen Kim Hwang Chen