Oblon, Spivak, McClelland, Maier & Neustadt
Semiconductor memory device having a BICMOS memory cell
 A semiconductor memory device includes a plurality of memory cells each having a bipolar transistor whose collector-emitter voltage V.sub.CE is controlled according to the base potential to satisfy the condition of I.sub.BE <I.sub.CB when the forward base current in the base-emitter path and the reverse base current in the collector-base path are respectively expressed by I.sub.BE and I.sub.CB and a switching element connected to the bipolar transistor, word lines, bit lines and emitter electrode lines connected to the memory cells, and functions as a dynamic memory cell in the data storing operation and as a gain memory cell in the readout operation. 
Kabushiki Kaisha Toshiba
G G G H
G11C G11C G11C H01L
inventional inventional inventional inventional
Fujio Shigeyoshi Tsuneaki Koji Takehiro
Masuoka Watanabe Fuse Sakui Hasegawa