Haynes and Boone, LLP
Grid refinement method
The present disclosure provide one embodiment of a method of a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel area S1 to generate a data grid having a second pixel area S2 that is equal to n2*S1, wherein the pattern generator includes a multi-segment structure having multiple grid segments, wherein the grid segments includes a first set of grid segments and a second set of grid segments, each of the first set of grid segments being configured to have an offset in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each of the second set of grid segments is controlled to have a time delay.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Wen-Chuan Pei-Yi Shy-Jay Burn Jeng Jaw-Jung
Wang Liu Lin Lin Shin