Pillsbury Winthrop Shaw Pittman LLP
Increasing a refresh period in a semiconductor memory device
In one method according to an embodiment of the invention, a reference bitline is biased and a refresh period of a DRAM cell is increased. In one example of such a method, biasing the reference bitline includes applying a predetermined bias voltage. In a memory device according to one embodiment of the invention, a bias circuit includes a bias capacitor connected to a bitline and configured and arranged to receive a bias signal.
Hynix Semiconductor Inc.
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Jung Pill
Kim