Nicholson De Vos Webster & Elliott LLP
Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features
Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements. The processor also includes a streamer element to prefetch the incoming operand set from two or more levels of a memory system.
Intel Corporation
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Kent D. Aamer Pratik M. Neal C. Samantika S. Chiachen Kermin Simon C. Michael C.
Glossop Jaleel Marolia Crago Sury Chou Fleming Steely, Jr. Adler