Harness, Dickey & Pierce, P.L.C.
Semiconductor memory device having improved refresh characteristics
A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.
SAMSUNG ELECTRONICS CO., LTD.
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Jung-sik Tae-seong Joo-sun Sang-ho Chan-yong Sung-min Jung-bae Cheol
Kim Jang Choi Shin Lee Yim Lee Kim