Method and apparatus for power optimization using don't care conditions of configuration bits in lookup tables
Various approaches for generating an implementation of an electronic circuit design are disclosed. In one approach, one or more configuration bits that have don't care conditions are identified for a LUT block of a design. A dynamic power state for a subset of a first level of logic devices in the LUT block is determined as a function of each identified configuration bit that has a don't care condition. A dynamic power state for a subset of a second level of logic devices is determined as a function of the determined power state for the first level of logic devices. A respective value for each identified configuration bit of the LUT is selected in response to the determined dynamic power states. The respective value is placed into the design for each identified configuration bit.
Xilinx, Inc.
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G06F G06F
additional inventional
Jason H. Subodh Kevin Qiang Tetse
Anderson Gupta Chung Wang Jang