Hayes, Soloway, Hennessey, Grossman & Hage, P.C.
Semiconductor memory device capable of improving read operation speed
 In a semiconductor memory device including a plurality of sense amplifiers arranged in rows, columns, a plurality of local data input/output line pairs, each pair being connected to one row of the sense amplifiers, a global data input/output line pair, a plurality of switches each connected between one of the local data input/output line pairs and the global data input/output line pair, and a differential amplifier connected to the global data input/output line pair, at least one pull-up circuit is connected to the global data input/output line pair. At least one of the switches is connected to the global data input/output line pair between the pull-up circuit and the differential amplifier. 
NEC Corporation
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inventional inventional inventional
Mamoru
Fujita