Oblon, McClelland, Maier & Neustadt, L.L.P.
Memory controller, information processing apparatus, and processor
According to one embodiment, a memory controller includes a nonvolatile cache memory and a controller. The nonvolatile cache memory is configured to store a piece of data stored in a nonvolatile main memory connected to the memory controller. The controller is configured to control writing of data to the nonvolatile cache memory. The memory controller is connected to a processor via an interconnect that ensures a protocol indicating a procedure for preventing data inconsistency in a plurality of cache memories. The controller causes, after detecting that the processor has updated data corresponding to any area of the nonvolatile main memory using the protocol, the updated data to be transmitted to the memory controller and writes the updated data to the nonvolatile cache memory.
TOSHIBA MEMORY CORPORATION
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Tatsunori Yusuke Masaya
Kanai Shirota Tarui