Jianq Chyun IP Office
Dual-gate, sonos, non-volatile memory cells and arrays thereof
Memory cells which include a semiconductor substrate having a source region and a drain region separated by a channel region; a charge-trapping structure disposed above the channel region of the semiconductor substrate; a first gate disposed above the charge-trapping structure and proximate to the source region; and a second gate disposed above the charge-trapping structure and proximate to the drain region; where the first gate and the second gate are separated by a first nanospace are provided, along with arrays including a plurality of such cells, methods of manufacturing such cells and methods of operating such cells.
Macronix International Co., Ltd.
H H H G H H H
H01L H01L H01L G11C H01L H01L H01L
inventional inventional inventional additional inventional inventional inventional
Kuang-Yeu Yen-Hao Erh-Kun Hang-Ting Chia-Hua
Hsieh Shih Lai Lue Ho