Crowell and Moring LLP
Efuse memory cell, eFuse memory array and using method thereof, and eFuse system
An eFuse memory cell, an eFuse memory array and a using method thereof, and an eFuse system are provided. In one form, an eFuse memory cell includes: a programming transistor, where a source of the programming transistor is grounded; a first electric fuse having a first terminal and a second terminal opposite to the first terminal, where the first terminal is connected to a drain of the programming transistor; one or more second electric fuses connected in parallel to each other, where each of the second electric fuses is connected in parallel with the first electric fuse, the second electric fuse has a third terminal and a fourth terminal opposite to the third terminal, and the third terminal is connected to the drain of the programming transistor; a word line connected to a gate of the programming transistor; a first programming bit line connected to the second terminal of the first electric fuse; and one or more second programming bit lines in a one-to-one correspondence with the second electric fuses, the second programming bit line being connected to the fourth terminal of the corresponding second electric fuse. The eFuse memory cell provided in the present disclosure has an opportunity to be programmed at least twice, thereby improving a yield rate of the eFuse memory array.
Semiconductor Manufacturing International (Beijing) Corporation Semiconductor Manufacturing International (Shanghai) Corporation
G G H G G G H
G11C G11C H01L G11C G11C G11C H01L
inventional inventional inventional inventional inventional inventional inventional
Xiaohua
Li