Haynes and Boone, LLP
Method of reducing a critical dimension of a semiconductor device
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate layer over a substrate, forming a hard mask layer over a gate layer, forming a first material layer over the hard mask layer, forming a patterned photoresist layer having an opening over the first material layer, etching the first material layer through a cycle including forming a second material layer over the semiconductor device and etching the first and second material layers, repeating the cycle until the hard mask layer is exposed by a reduced opening, the reduced opening formed in a last cycle, etching the hard mask layer beneath the second opening to expose the gate layer, and patterning the gate layer using the hard mask layer. An etching selectivity of the first and second material layers is smaller than an etching selectivity of the second material layer and the photoresist layer.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Yih-Ann Chao-Cheng Weng Ryan Chia-Jen De-Fang Yu Chao Chia-Wei
Lin Chen Cheng Chen Chen Lin Chang