Michael J. Chang, LLC
Vertical transistors with different gate lengths
Techniques for forming VFETs with differing gate lengths are provided. In one aspect, a method for forming a VFET device includes: patterning fins in a substrate, wherein at least one of the fins includes a vertical fin channel of a FET1 and at least another one of the fins includes a vertical fin channel of a FET2; forming a bottom source and drain; forming bottom spacers on the bottom source and drain; forming gates surrounding the vertical fin channel of the FET1 and FET2; forming top spacers on the gate; and forming top source and drains at the tops of the fins by varying a positioning of the top source and drains relative to at least one of the vertical fin channel of the FET1 and the FET2 such that the FET1/FET2 have an effective gate length Lgate1/Lgate2, wherein Lgate1>Lgate2. A VFET device is also provided.
International Business Machines Corporation
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Chen Juntao Xin Kangguo
Zhang Li Miao Cheng