Marger Johnson & McCollom, P.C.
Semiconductor memory device and method of arranging a decoupling capacitor thereof
A semiconductor memory device with improved operational performance by reducing the level variation of first and second power voltages applied to a sense amplifier by efficiently locating a decoupling capacitor. The decoupling capacitor is arranged on an empty region of a plurality of the first and second sense amplifiers and connected between the first and second power voltage lines. A plurality of global data I/O line pairs is arranged perpendicular to the direction of a plurality of local data I/O line pairs.
Samsung Electronics Co., Ltd.
G
G11C
inventional
Hyung-Chan Chi-Wook
Choi Kim