McClure, Qualey & Rodack, LLP
Method for reducing core-to-core mismatches in SOC applications
Methods for reducing core-to-core mismatch are provided. The method includes measuring gate lengths of a representative pattern of each core in a first lot of SOC products by a measurement apparatus. Each of the SOC products in the first lot includes more than two cores identical to each other. The method also includes determining tuning amounts according to the differences between the gate lengths of each core, and adjusting manufacturing conditions for critical dimensions of gate length of each core in a second lot of SOC products respectively according to the tuning amounts for reducing core-to-core mismatch due to the surrounding environment of each core. Each of the SOC products in the second lot includes more than two cores identical to each other and also identical to the cores in the first lot.
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H H
H01L H01L
inventional inventional
Shih-Che Chia-Ming Sheng-Tang Chao-Jui
Lin Chang Wang Wang