Eschweiler & Potashnik, LLC
Interconnect landing method for RRAM technology
The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit has a first inter-level dielectric (ILD) layer over a substrate. A lower electrode is over the first ILD layer, a data storage structure is over the lower electrode, and an upper electrode is over the data storage structure. An upper interconnect wire directly contacts an entirety of an upper surface of the upper electrode. A conductive via directly contacts an upper surface of the upper interconnect wire. The conductive via has an outermost sidewall that is directly over the upper surface of the upper interconnect wire.
Taiwan Semiconductor Manufacturing Co., Ltd.
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Jen-Sheng Yu-Wen Kuo-Chi Chih-Yang Wen-Ting Chin-Chieh Hsia-Wei
Yang Liao Tu Chang Chu Yang Chen