Eschweiler & Associates, LLC
Process of ultra thick trench etch with multi-slope profile
The present disclosure relates to an integrated chip (IC) having an ultra-thick metal layer formed in a metal layer trench having a rounded shape that reduces stress between an inter-level dielectric (ILD) layer and an adjacent metal layer, and a related method of formation. In some embodiments, the IC has an inter-level dielectric layer disposed above a semiconductor substrate. The ILD layer has a cavity with a sidewall having a plurality of sections, wherein respective sections have different slopes that cause the cavity to have a rounded shape. A metal layer is disposed within the cavity. The rounded shape of the cavity reduces stress between the ILD layer and the metal layer to prevent cracks from forming along an interface between the ILD layer and the metal layer.
Taiwan Semiconductor Manufacturing Co., Ltd.
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inventional inventional additional inventional inventional
Shao-Yu Wei-Te Kuan-Chi Chun-Liang Chih-Hung
Chen Wang Tsai Fan Hsueh