Wagner, Murabito & Hao LLP
Partitioned shift right logic circuit having rounding support
A partitioned shift right logic circuit that is programmable and contains rounding support. The circuit of the present invention accepts a 32-bit value and a shift amount and then performs a right shift operation on the 32-bits and automatically rounds the result(s). Signed or unsigned values can be accepted. The right shift circuit is partitioned so that the 32-bit value can represent: (1) a single 32-bit number; or (2) two 16-bit values. A 1 bit selection input indicates the particular partition format. In operation, if the input value is not negative, then one ("1") is added at the guard bit position and a right shift with truncate is performed. If the input is negative and the guard bit is zero, then no addition is done and a right shift with truncate is performed. If the input is negative and the guard bit is one and the sticky bit is zero, then no addition is done and a right shift with truncate is performed. If the input is negative and the guard bit is one and the sticky bit is one, then one is added at the guard bit position and a right shift with truncate is performed. The shift circuitry used by the present invention is fully partitioned to accept word or half-word input and contains multiple cascaded multiplexer stages for performing partitioned right shifting and supports signed shifting. Each multiplexer stage can be programmed to perform a selected shift amount (including 0 shift). The right shift circuit of the present invention can be used in multi-media applications and can also be used for general purpose and VLIW (very long instruction word) processor without performance degradation.
Sony Corporation of Japan Sony Electronics, Inc.
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inventional additional additional inventional
Farzad Aamir Alam Vojin G. Wei-Jen Andy W.
Chehrazi Farooqui Oklobdzija Li Yu