Blakely, Sokoloff, Taylor & Zafman
Method and apparatus for cache memory replacement line identification
 A method and apparatus for cache memory replacement line identification have a cache interface which provides a communication interface between a cache memory and a controller for the cache memory. The interface includes an address bus, a data bus, and a status bus. The address bus transfers requested addresses from the controller to the cache memory. The data bus transfers data associated with requested addresses from the controller to the cache memory, and also transfers replacement line addresses from the cache memory to the controller. The status bus transfers status information associated with the requested addresses from the cache memory to the controller which indicate whether the requested addresses are contained in the cache memory. In one embodiment, the data bus also transfers cache line data associated with a requested address from the cache memory to the controller when the requested address hits the cache memory. 
Intel Corporation
G G
G06F G06F
inventional additional
John M. Wen-Hann Nitin V. Michael W. Gurbir
Bauer Wang Sarangdhar Rhodehamel Singh