Write per bit with write mask information carried on the data path past the input data latch
 A dynamic random access memory part 30 provides a write per bit feature by locating the respective write mask information latches 118 adjacent the respective local I/O buffers 116. The write mask information thus passes through the data latch 108 and across the data path to the local I/O buffer 116 before being latched. This reduces the area otherwise needed for the additional write mask lead, which in a x8, x16, x32 or x64 bit part can be intolerably large. 
Texas Instruments Incorporated
G
G11C
inventional
Michael Scott E. Duy-Loan T.
Ho Smith Le