Eschweiler & Potashnik, LLC
Memory layout for reduced line loading
Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.
Taiwan Semiconductor Manufacturing Co., Ltd.
G H G G G G G H G H H G H H H G H G G G G G G H
G11C H01L G11C G11C G11C G11C G11C H01L G11C H01L H01L G11C H01L H01L H01L G11C H01L G11C G11C G11C G11C G11C G11C H01L
inventional inventional additional inventional inventional inventional additional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional inventional additional inventional inventional inventional
Wen-Ting Chih-Yang
Chu Chang