Semiconductor memory device and a data reading method and a data writing method therefor
 A memory device to perform a plurality of data transfers during a single memory cycle without extending the cycle time for memory access, and to enhance the data transfer rate. A memory array 1 has a plurality of word lines, a plurality of bit lines divided into a predetermined number of groups, and a plurality of memory cells. The bit lines are grouped based on a residue obtained by dividing a column address designating a bit line by the number of groups. The column address decoder 4 generates column addresses of the group number in accordance with the column address signal and an access order signal designating the access order for the groups. When the access order signal designates the ascending order, the bit line selection means 3 generates sequential column addresses, in a number equivalent to the group number and in the ascending order, with the column address signal serving as a reference. When the access order signal designates the descending order, the bit line selection means 3 generates sequential column addresses, in a number equivalent to the group number and in a descending order, with the column address signal serving as a reference. 
International Business Machines Corporation
G G
G11C G11C
inventional inventional
Yolaro Noritoshi Hisatada Masahiro
Mori Yamasaki Miyatake Tanaka