Method of and circuit for verifying a layout of an integrated circuit device
A method of verifying a layout of an integrated circuit device is disclosed. The method comprises steps of receiving a physical layout for a schematic of a circuit implemented in the integrated circuit device; generating an implant table file having data showing a relationship between layers and device types of the integrated circuit device; and generating a layout-versus-schematic rules file using the implant table file.
Xilinx, Inc.
G
G06F
inventional
Min-Fang
Ho