Oblon, Fisher, Spivak, McClelland & Maier
Address decoder
 An address decoder comprises an OR circuit and a NOR circuit, the OR circuit having switching transistors to which decoder inputs and a chip enable signal are applied, a load transistory and a transistor for precharging a common precharge node by the complementary chip enable signal. The output of this OR circuit is applied to the NOR circuit with the complementary chip enable signal, the set-up time of the decoder or the NOR circuit being independent of the number of decoder inputs. 
Tokyo Shibaura Electric Co., Ltd.
H
H03K
inventional
Ochii Yasoji
Kiyofumi Suzuki