Marger Johnson & McCollom, P.C.
Arrangement of bitline boosting capacitor in semiconductor memory device
A semiconductor memory device includes first and second isolation transistors for electrically connecting/isolating a pair of bitlines to/from a sense amplifier circuit, and a MOS transistor having a source region that is shared with one of sources of the first and second isolation transistors. The MOS transistor may be used as a bitline boosting capacitor.
Samsung Electronics Co., Ltd.
G G H
G11C G11C H01L
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Yun-Sang Jae-Hoon Sang-Seok Jong-Hyun
Lee Joo Kang Choi