Jaffery Watson Mendonsa & Hamilton LLP
Extend GPU/CPU coherency to multi-GPU cores
In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.
INTEL CORPORATION
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Balaji Chandrasekaran Tsung-Han Abhishek R. Ben J. Feng Justin E. Altug Narayan Prasoonkumar John C. Sara S. Kamal Joydeep Nicolas C. Eriko Rajkishore
Vembu Sakthivel Lin Appu Ashbaugh Chen Gottschlich Koker Srinivasa Surti Weast Baghsorkhi Sinha Ray Galoppo Von Borries Nurvitadhi Barik