Caching support for direct memory access address translation
An embodiment of the present invention is a technique to provide cache support for direct memory access address translation. A cache structure stores cached entries used in address translation of a guest physical address to a host physical address. The guest physical address corresponds to a guest domain identified by a guest domain identifier in an input/output (I/O) transaction requested by an I/O device. A register stores an invalidating domain identifier identifying an invalidating domain and an indicator indicating invalidating an entry in the cached entries having a tag.
Intel Corporation
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Richard Balaji Gilbert Rajesh Ioannis
Uhlig Vembu Neiger Madukkarumukumana Schoinas