Miles & Stockbridge P.C.
Semiconductor device
The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL.
Renesas Technology Corporation Hitachi, ULSI Systems Co., Ltd.
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Takao Yusuke Takeshi Nobuhiro Hiroyuki
Watanabe Kanno Sakata Oodaira Mizuno