Sherr & Jiang, PLLC
Vertically pinched junction field effect transistor
A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a main-channel region formed between the source region and the drain region, a well region formed on the main-channel region between the source region and the drain region, vertical pinch-off regions formed at both source and drain ends or only on the source-end of the well region on the main-channel region in the source region and the drain region respectively, a source contact on the vertical pinch-off region in the source region, a drain contact on the vertical pinch-off region in the drain region, a gate contact on the well region between the source contact and the drain contact and shallow trench isolations formed on the well region.
Dongbu HiTek Co., Ltd.
H H
H01L H01L
inventional inventional
Kyu Ok Badih Joo Hyung Jung Joo
Lee El-Kareh Kim Kim