Schwabe, Williamson & Wyatt P.C.
Forming III-V device structures on (111) planes of silicon fins
Methods of forming high voltage (111) silicon nano-structures are described. Those methods and structures may include forming a III-V device layer on (111) surface of a silicon fin structure, forming a 2DEG inducing polarization layer on the III-V device layer, forming a source/drain material on a portion of the III-V device layer on terminal ends of the silicon fin. A middle portion of the silicon fin structure between the source and drain regions may be removed, and backfilled with a dielectric material, and then a gate dielectric and a gate material may be formed on the III-V device layer.
Intel Corporation
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Sansaptak Sanaz Han Wui Benjamin Seung Hoon Marko Robert
Dasgupta Gardner Then Chu-Kung Sung Radosavljevic Chau