Limbach, Limbach & Sutton
Method for making electrically programmable memory device by doping the floating gate by implant
 In the present invention, asperity in the floating gate of an EPROM or EEPROM device is reduced. An improved process for fabricating ultrahigh coupling interpoly isolation dielectrics comprising a structure of oxide-nitride-oxide is disclosed. The first oxide is grown on undoped LPCVD polycrystalline silicon (polysilicon) to reduce the grain boundary-oxidation enhancement effect at the interface of floating gate polysilicon and interpoly oxide. This results in much higher breakdown capability of interpoly dielectrics. As a consequence, the shrinkage of the interpoly electrical thickness to an extent far beyond current limitation becomes possible. Implanted dopants through interpoly oxide into the floating gate polysilicon also eliminate the oxidation enhanced diffusion from conventional POCl.sub.3 doped polysilicon into tunnel oxide. The phosphorus induced trap in the tunnel oxide region are reduced. The EEPROM threshold window can remain open beyond 10.sup.6 cycles. 
Exel Microelectronics, Inc.
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Chun Arun K. Thomas T. L.
Ho Malhotra Chang