Recessed structure for shallow trench isolation and salicide process
 A shallow trench isolated FET LDD structure that has a low probability of short circuiting at the silicon to trench interface or between the source or drain and the gate (because of a titanium silicide bridge) is described. It is based on an isolation trench having a top portion with vertical sides and a lower portion with sloping sides. With the filled trench in place, along with a polysilicon gate and gate oxide, the thinner, lightly doped, N type layer is formed using ion implantation. Spacers are then formed on the gate but, prior to the second ion implant step, a few hundred Angstroms of silicon is selectively removed from the surface. This causes the trench filler material to extend above the wafer surface and the spacers to extend above the gate. A deeper, more strongly N-type, layer is then formed in the usual way, followed by the standard SALICIDE process for making contact to source, gate, and drain. 
Taiwan Semiconductor Manufacturing Company, Ltd.
H
H01L
inventional
Sheng-Jyh Jing-Meng Chao-Chieh
Wu Liu Tsai