Miles & Stockbridge P.C.
Three-transistor pipelined dynamic random access memory
A semiconductor device includes a plurality of DRAM memory cells each having first, second, and third MOS transistors; a plurality of first word lines coupled to the gates of the first MOS transistors; a plurality of second word lines coupled to the gates of the second MOS transistors; a plurality of first bit lines coupled to the source/drain paths of the first MOS transistors; and a plurality of second bit lines coupled to the source/drain paths of the second MOS transistors. The plurality of DRAM memory cells includes a series of such memory cells defining a plurality of groups of k memory cells, and the plurality of first word lines includes a group of k first word lines, each of which is coupled to a gate of a first MOS transistor only in every kth DRAM memory cell of the series, wherein k is greater than one.
Hitachi, Ltd.
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Hiroyuki Takao Satoru
Mizuno Watanabe Akiyama