Interface circuit of video signal hard copy apparatus
 An interface circuit of video signal hard copy apparatus for optimizing a phase of a sampling clock to an image signal. A delayed signal of a video sync signal is employed for a reference input signal of a sampling clock generation circuit. The delay quantity of the video sync signal is arbitrarily set by a control circuit. The delay quantity corresponding to the point of change of sampled data is detected by a CPU circuit according to the sequential comparison with some of the sampled data of an image signal in the plural delay quantities. A stable sampling can be attained even for a high frequency video signal exceeding 100 MHz by setting the optimum delay quantity according to the detected delay quantity. 
Seiko Instruments & Electronics Ltd.
G G
G06K G06K
additional inventional
Kaneo Yoshio Fumihiro Kenichi Shinya
Yamaguchi Shimada Tanaka Matsushima Watanabe