Fleit Intellectual Property Law
Method and structure for forming vertical transistors with various gate lengths
Various methods and structures for fabricating a plurality of vertical fin FETs on the same semiconductor substrate in which a first gate length of a first gate in a first vertical fin FET is less than a second gate length of a second gate in a second vertical fin FET. A difference in gate lengths between different vertical fin FETs can be precisely fabricated by using atomic layer silicon germanium epitaxy. Gate length offset is formed at a bottom source/drain junction region of each vertical fin FET transistor, which allows downstream processing for all vertical fin FET transistors to be the same.
International Business Machines Corporation
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Shogo Choonghyun Juntao Kangguo
Mochizuki Lee Li Cheng