Eschweiler & Potashnik, LLC
Method and apparatus for reading RRAM cell
In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.
Taiwan Semiconductor Manufacturing Co., Ltd.
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Sheng-Hung Chin-Chieh Chih-Yang Manish Kumar Chi-Tsai Kuo-Chi Jen-Sheng Hsia-Wei Wen-Ting Chang-Sheng
Shih Yang Chang Singh Chen Tu Yang Chen Chu Liao