Slater & Matsil, L.L.P.
Method for forming high-drain-voltage tolerance MOSFET transistor in a CMOS process flow with double well dose approach
A method for forming a high-voltage drain metal-oxide-semiconductor (HVD-MOS) device includes providing a semiconductor substrate; forming a well region of a first conductivity type; and forming an embedded well region in the semiconductor substrate and only on a drain side of the HVD-MOS device, wherein the embedded region is of a second conductivity type opposite the first conductivity type. The step of forming the embedded well region includes simultaneously doping the embedded well region and a well region of a core regular MOS device, and simultaneously doping the embedded well region and a well region of an I/O regular MOS device, wherein the core and I/O regular MOS devices are of the first conductivity type. The method further includes forming a gate stack extending from over the embedded well region to over the well region.
Taiwan Semiconductor Manufacturing Company, Ltd.
H Y H H H
H01L Y10S H01L H01L H01L
inventional additional inventional inventional inventional
Chih-Sheng Chih-Ping Yung Chih Michael
Chang Chao Tsai Yu