Gibb I.P. Law Firm, LLC
Balancing NFET and PFET performance using straining layers
An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
Chartered Semiconductor Manufacturing Ltd. Freescale Semiconductor, Inc. International Business Machines Corporation Infineon Technologies North America Corp.
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inventional inventional
Anda C. Haizhou Melanie J. Weipeng Jin-Ping Voon-Yew Da Yong Meng Franck Young Way Dae-Gyu Kenneth J. Laegu Xiangdong
Mocuta Yin Sherony Li Han Thean Zhang Lee Arnaud Teh Park Stein Kang Chen