Package on-package devices with multiple levels and methods therefor
Package-on-package (“PoP”) devices with multiple levels and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. First and second conductive lines are coupled to the upper surface of the package substrate respectively at different heights in a fan-out region. A first molding layer is formed over the upper surface of the package substrate. A first and a second wafer-level packaged microelectronic component are located above an upper surface of the first molding layer respectively surface mount coupled to a first and a second set of upper portions of the first conductive lines. A third and a fourth wafer-level packaged microelectronic component are located above the first and the second wafer-level packaged microelectronic component respectively surface mount coupled to a first and a second set of upper portions of the second conductive lines.
Invensas Corporation
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Wael Ashok S. Hoki Zhuowen Min Belgacem
Zohni Prabhu Kim Sun Tao Haba