McClure, Qualey & Rodack, LLP
Device and method for robustness verification
A device includes a fault generation circuit and a first fault injection circuit. The fault generation circuit is configured to generate a fault signal and a plurality of control signals according to a mode signal. The first fault injection circuit is configured to inject a first final fault signal to an under-test device based on the fault signal and the plurality of control signals, in order to verify robustness of the under-test device.
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
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inventional inventional inventional inventional
Sandeep Kumar Yun-Han Stanley Ji-Jan
Goel Lee John Chen