McClure, Qualey & Rodack, LLP
Semiconductor metrology target and manufacturing method thereof
A metrology target of a semiconductor device is provided. The metrology target includes a substrate including first and second layers. The first layer includes a first grating, a second grating, and a first dummy structure. The first dummy structure is at least formed between the first grating and the second grating. The second layer is formed over the first layer and includes a third grating and a fourth grating. The first, second, third and fourth gratings are formed based on the first spatial period. The third grating and fourth grating are placed to overlap the first grating and second grating, respectively. The first grating and the third grating are formed with a first positional offset which is along a first direction. The second grating and the fourth grating are formed with a second positional offset which is along a second direction which is opposite to the first direction.
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
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Yu-Ching Kuei-Shun Long-Yi Jia-Hong Po-Chung Hsin-Chin Kai-Hsiung Hsiang-Yu Yun-Heng Chi-Kang
Wang Chen Chen Chu Cheng Lin Chen Su Tseng CHang