SRAM including bottom gate transistor
Bit lines in SRAM array are multi-divided, so that a segment read circuit is connected to local bit line, which circuit serves as amplifying transistor of an amplifier with load device of a block read circuit. Thus the amplified voltage is latched by a current mirror which serves as another amplifier in the block read circuit, such that one data is latched early but another data is latched later because the amplifier changes its output quickly or slowly depending on the local bit line voltage. In this manner, time-domain sensing scheme is introduced to differentiate fast data and slow data, where the locking signal is generated by a read enable signal or a reference signal based on fast data. Particularly, memory cell includes bottom gate transistor as a pull-up device to reduce area. Additionally, alternatives are described, such as stacked memory cell structure and CAM application.
G
G11C
inventional
Juhan
Kim