The Neudeck Law Firm, LLC
Memory system with calibrated data communication
An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
Rambus Inc.
G G G H G G H G G G G G G G G G
G06F G06F G06F H04L G06F G06F H04L G06F G06F G06F G06F G06F G06F G06F G11C G06F
inventional inventional inventional additional inventional inventional inventional additional inventional inventional additional inventional inventional inventional inventional inventional
Stefanos Tsyr-Chyang Jun Mark A. Jared LeVan Kevin S. Leung Roxanne Donald C. Benedict Chung-Kwong Bruno W.
Sidiropoulos Ho Kim Horowitz Zerbe Donnelly Yu Vu Stark Lau Garlepp