William Park & Associates Ltd.
Digital phase locked loop having insensitive jitter characteristic for operating circumstances
Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.
Electronics and Telecommunications Research Institute
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Woo Young Bhum Cheol Seung Woo Kwang Chun
Choi Lee Lee Choi