Withrow & Terranova
Back gate biasing magneto-resistive random access memory (MRAM) bit cells to reduce or avoid write operation failures caused by source degeneration
Back gate biasing magneto-resistive random access memory (MRAM) bit cells to reduce or avoid write operation failures caused by source degeneration are disclosed. In one aspect, an MRAM bit cell includes a magnetic tunnel junction (MTJ) device and an access transistor used to control reading and writing of the MRAM bit cell. To reduce or avoid source degeneration caused by a voltage at a source region of the access transistor in response to a write operation, a back gate bias voltage is applied to a back gate electrode of the access transistor, the back gate bias voltage controlled to be greater than or equal to a back gate voltage associated with the access transistor having a nominal threshold voltage corresponding to operation without source degeneration plus a voltage corresponding to the source region of the access transistor.
QUALCOMM Incorporated
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Seung Hyuk Xia
Kang Li