Wafer level chip scale package having continuous through hole via configuration and fabrication method thereof
A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.
POWERTECH TECHNOLOGY INC.
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Hung-Hsin Chia-Chang Wen-Hsiung Li-Chih Kee-Wei Chia-Wen
Hsu Chang Chang Fang Chung Lien