Womble Carlyle Sandridge & Rice, LLP
Configurable memory block
Circuits for a memory array and a method of operating a configurable memory block are disclosed. An embodiment of the disclosed memory circuits includes a first memory block coupled to a second memory block to form an array of memory blocks. Each of the memory blocks has multiple bit lines with a dedicated address decoder coupled to the bit lines from each of the memory blocks. Switches are placed in between the first and second memory blocks such that each of the bit lines from the first memory block is connected to a corresponding bitline from the second memory block through one of the switches. The switches may be used to either connect the second memory block to the first memory block or disconnect the second memory block from the first memory block.
Altera Corporation
G
G11C
inventional
Eu Geen Zun Yang Boon Jin Wei Yee Tat Mun
Chew Tan Ang Koay Lui