Hauptman Ham, LLP
Clock duty cycle adjustment and calibration circuit and method of operating same
A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to a first phase clock signal, a second phase clock signal and a set of control signals, and adjust the second duty cycle responsive to the set of control signals or a phase difference between the first phase clock signal and the second phase clock signal. The calibration circuit is configured to perform a duty cycle calibration of a second duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
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H03C H03C G06F H03L H03K H03K H03K
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Tien-Chien
Huang