Method and circuits for localizing defective interconnect resources in programmable logic devices
Described are methods and circuits for identifying defective device layers and localizing defects. Production PLD tests extract statistically significant data relating failed interconnect resources to the associated conductive metal layer. Failure data thus collected is then analyzed periodically to identify layer-specific problems. Test circuits in accordance with some embodiments employ interconnect resources heavily weighted in favor of specific conductive layers to provide improved layer-specific failure data. Some such test circuits are designed to identify open defects, while others are designed to identify short defects.
Xilinx, Inc.
H G G G
H03K G01R G01R G01R
inventional inventional inventional inventional
Zhi-Min Xiao-Yu David Yuezhen
Ling Li Mark Fan