Slater Matsil, LLP
Voids in STI regions for forming bulk FinFETs
An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Hung-Ming Feng Chih Chieh Tsung-Lin
Chen Yuan Yeh Lee