Schwegman, Lundberg, Woessner & Kluth, P.A.
Delay locked loop control circuit
A memory device includes delay locked loop that generates an internal signal based on an external signal. The internal signal serves a reference clock signal for most modes operations of the memory device. In a self refresh mode, the delay locked loop is completely deactivated to completely deactivate the internal signal. In a non-self refresh mode, the delay locked loop is periodically deactivated to periodically deactivate the internal signal based on certain modes of operations of the memory device.
Micron Technology, Inc.
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Wen Mark R.
Li Thomann