Onello & Mello, LLP
DRAM controller having DRAM bad page management function and bad page management method thereof
A bad page management system is provided to guarantee a yield of a volatile semiconductor memory device such as a DRAM. A bad page list exists in a DRAM. A page remapper in a memory controller performs a page remapping operation in parallel with a normal operation of a scheduling unit to perform a latency overhead hidden function. A chip size of the DRAM is reduced or minimized. A DRAM controller performs a latency overhead hidden function to control a DRAM.
Samsung Electronics Co., Ltd.
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G11C G11C G11C G06F G11C
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Jaeyoun Haksoo Sung Hyun Jun Hee Hyojin Sua Dongsoo
Youn Yu Lee Yoo Choi Kim Kang