Low inductance MLC capacitor with metal impregnation and solder bar contact
 A laminated capacitor is joined to the surface of a chip carrier for large scale integrated circuit chips. The capacitor lies adjacent to positions where chips are located. The capacitor includes a plurality of capacitor plates. The capacitor is bonded to the chip carrier with an array of solder bars comprising an elongated strip of metallic material. Each of the bars is connected to a set of the capacitor plates in the laminated capacitor by means of tab connections on the plates, whereby each of the plates is connected by a plurality of tabs to a plurality of the solder bars. Methods of fabrication of the laminated capacitor structure and solder bars are described. 
International Business Machines Corporation
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H05K H01G Y02P H05K Y10T
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Chung W. Timothy C. Dudley A.
Ho Reiley Chance