Muir Patent Law, PLLC
Semiconductor package having a molding layer including a molding cavity and method of fabricating the same
Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package comprises a lower semiconductor chip on a lower substrate, a lower molding layer covering the lower semiconductor chip on the lower substrate and including a molding cavity that extends toward the lower semiconductor chip from a top surface of the lower molding layer, an interposer substrate on the top surface of the lower molding layer and including a substrate opening that penetrates the interposer substrate and overlaps the molding cavity, and an upper package on the interposer substrate. The molding cavity has a floor surface spaced apart from the upper package across a substantially hollow space.
SAMSUNG ELECTRONICS CO., LTD
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Sung-Kyu Sangsoo Pyoungwan Yun-Young Junwoo Insup Seung Hwan Hyunki
Park Kim Kim Kim Park Shin Kim Kim