Jianq Chyun IP Office
Method for manufacturing memory cell
The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.
Macronix International Co., Ltd.
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Chia-Hua Hang-Ting Erh-Kun Tzu-Hsuan
Ho Lue Lai Hsu