Electronic design automation tool for the design of a semiconductor integrated circuit chip
 An electronic design automation tool embodiment uses a single slack graph structure throughout a process to provide communication between a placer (performing placement) and a timing constraint generator (performing slack distribution). The tool includes a slack graph generator, a timing calculator, a timing analyzer, a timing constraint generator and a net bounding box generator. A list of net constraints and a list of complete path constraints are fed to the slack graph generator during operation. Timing calculations from the delay calculator and zero net RC delays from a clustering process in a placer also provide input to the slack graph generator. The list of net constraints, a list of pin-to-pin constraints and a set of specifications for system clocking are input to the timing analyzer. The timing constraint generator receives a composite slack graph from the timing calculator, slack graph generator and timing analyzer. A refined slack graph is output to the net timing constraint generator for mincut placement and placement on an iterative basis. The net timing constraint can be presented in many format, such as limit on net bounding box. 
Arcsys, Inc.
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G06F G06F
inventional inventional
Chwen-Cher Ren-Song
Chang Tsay