Fish & Richardson P.C.
Semiconductor device, memory device, and electronic device
A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.
Semiconductor Energy Laboratory Co., Ltd.
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Shunpei Tatsuya Kiyoshi Takanori
Yamazaki Onuki Kato Matsuzaki