Methods and structures for compensating and tracking process, voltage and temperature variations
An integrated circuit having a clock synchronizing circuit is described. The clock synchronizing circuit includes an input-output buffer and a plurality of sampling buffer circuits. The input-output buffer receives an input signal and generating an output signal. Each sampling buffer circuit receives the output signal and a sampling clock signal. Each sampling buffer circuit generates a first sampled output by sampling the output signal at the rising edge of the corresponding sampling clock signal and a second sampled output by sampling the output signal on the falling edge of the corresponding sampling clock signal. The sampling clock signal has a predetermined phase difference at each of the plurality of sampling buffer circuits.
Altera Corporation
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H04L G06F H04L G06F
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Chi Mun Kin Hong
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