Trop, Pruner & Hu, P.C.
System, apparatus and method for segmenting a memory array
In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
Intel Corporation
G G G G G G G G G Y G G G G G G G G G
G11C G06F G11C G06F G11C G06F G06F G06F G06F Y02D G06F G06F G06F G06F G11C G06F G06F G06F G06F
inventional additional inventional additional additional additional additional inventional additional additional additional additional additional additional inventional inventional additional additional inventional
Altug Bhushan M. Abhishek R. Sunil Anupama A. Iqbal R.
Koker Borole Appu Nekkanti Thaploo Rajwani