Slater & Matsil, L.L.P.
Bond pad scheme for Cu process
A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.
Taiwan Semiconductor Manufacturing Company, Ltd.
H H H H H H H H H H H H H H H H H H H H H H H H H H
H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L
additional additional additional additional additional inventional additional inventional additional additional additional additional additional inventional additional additional additional additional inventional additional additional additional additional additional additional additional
Huan-Chi Chin-Tien Chia-Hung Jiunn-Jyi Yu-Hua Tzong-Sheng Min
Tseng Yang Lai Lin Lee Chang Cao