Blakely, Sokoloff, Taylor & Zafman LLP
Cache memory with reduced latency
 The present invention provides a method and a data processing system for accessing a memory of a data processing system, the data processing system including a first and at least a second level memory for storing information. The method includes issuing a memory request to the first level memory, and issuing the memory request to the second level memory at substantially the same time the memory request is issued to the first level memory. 
Intel Corporation
G G
G06F G06F
inventional inventional
Cheng-Feng Harsh Gunjeet D.
Chang Kumar Baweja