McDermott, Will & Emery
DRAM memory cell with dummy lower electrode for connection between upper electrode and upper layer interconnect
In a DRAM memory cell that is a semiconductor memory device, a bit line connected to a bit line plug and local interconnect are provided on a first interlayer insulating film. A contact is not provided on a Pt film constituting an upper electrode, and a dummy lower electrode is in direct contact with a dummy barrier metal. That is, the upper electrode is connected to upper layer interconnect (Cu interconnect) by the dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, deterioration of characteristics of a capacitive insulating film can be prevented.
Matsushita Electric Industrial Co., Ltd.
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inventional inventional additional
Akihiko Hisashi Yoshihiro
Tsuzumitani Ogawa Mori