Systems and methods for reconfiguring cache memory
A microprocessor system is disclosed that includes a first data cache that is shared by a first group of one or more program threads in a multi-thread mode and used by one program thread in a single-thread mode. A second data cache is shared by a second group of one or more program threads in the multi-thread mode and is used as a victim cache for the first data cache in the single-thread mode.
NXP USA, Inc.
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Y02D G06F G06F G06F G06F
additional additional inventional inventional inventional
Thang M.
Tran