Jaffery Watson Mendonsa & Hamilton, LLP
Page faulting and selective preemption
One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.
Intel Corporation
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David Abhishek R. Prasoonkumar Balaji Joydeep Murali Ingo Altug Guei-Yuan Subramaniam M.
Puffer Appu Surti Vembu Ray Ramadoss Wald Koker Lueh Maiyuran