Fabrication process for MOSFET devices and a reproducible capacitor structure
 A process has been developed in which a capacitor structure can be simultaneously fabricated with NFET and PFET to be used in EEPROM, SRAM or DRAM cells. The process features the use of a silicon nitride layer, protecting an underlying capacitor dielectric layer from an oxidation ambient, presented during a subsequent NFET source and drain drive-in procedure. 
Taiwan Semiconductor Manufacturing Company, Ltd.
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H01L H01L
inventional inventional
Tzong-Sheng Chen-Cheng
Chang Chou