Method and apparatus for improving a circuit layout using a hierarchical layout description
Various approaches for improving an integrated circuit layout. In one approach, a tree-type hierarchical layout representation of the circuit design is traversed. At each block visited during the traversing, a process determines whether there exists an improvement opportunity for each cell associated with the block. In response to determining that an improvement opportunity exists for a cell of a first block of the plurality of blocks, the process determines whether a modification to the cell satisfies one or more rules for every other block of the block type of the first block in the hierarchical representation. If the rules are satisfied, the modification is stored. Otherwise, the modification is discarded.
Xilinx, Inc.
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Y02P G06F G06F
additional inventional additional
Min-Fang Min-Hsing Peter Michael J. Zhiyuan Jane W. Peter
Ho Chen Hart Wu Sowards Rabkin