Morrison & Foerster LLP
Semiconductor memory device and portable electronic apparatus
A semiconductor memory device includes a control logic circuit for generating read selection signals each selecting one plane for reading and write selection signals each selecting one plane for writing from a plurality of planes in which memory cells are arranged in an array, an address selection circuit disposed for each of the planes, and an address buffer circuit for simultaneously providing a write address and a read address. Each of the address selection circuits is configured so as to be able to receive one of the read selection signals and one of the write selection signals from the control logic circuit. The memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.
Sharp Kabushiki Kaisha
G G H G H G H
G11C G11C H01L G11C H01L G11C H01L
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Hiroshi Akihide Yoshinao Masaru
Iwata Shibata Morikawa Nawaki