Slater & Matsil, L.L.P.
Reducing voltage drops in power networks using unused spaces in integrated circuits
A method of designing an integrated circuit includes providing an integrated circuit design including a power network. A voltage drop mitigation system is provided, which includes a power strap enhancer configured to automatically find a source node and a terminal node in the power network. A redundant strap for the power network using the voltage drop mitigation system is added, wherein the redundant strap interconnects the source node and the terminal node. After the step of adding the redundant strap, dummy patterns may be added.
Taiwan Semiconductor Manufacturing Company, Ltd.
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G06F G06F
additional inventional
Wen-Hao Chung-Sheng Yun-Han Mark Shane Dinesh
Chen Yuan Lee Peng Baviskar