IP & T Group LLP
Integrated circuit
An integrated circuit includes a delay locked loop configured to delay a reference clock signal by a delay time for delay locking and generate a delay locked clock signal, a clock transmission circuit configured to transmit the delay locked clock signal in response to a clock transmission signal, a duty correction circuit configured to perform duty correction operation on an output clock signal of the clock transmission circuit, and a clock transmission signal generation circuit configured to generate the clock transmission signal in response to a command and burst length information.
Hynix Semiconductor Inc.
H
H03L
inventional
Hae-Rang Yong-Ju Jae-Min Seong-Jun
Choi Kim Jang Lee