Conley, Rose & Tanyon, PC
Microprocessor configured to selectively invoke a microcode DSP function or a program subroutine in response to a target address value of branch instruction
 A microprocessor having a microcode unit is provided. Routines comprising DSP functions and instruction emulation routines are stored within a read-only memory within the microcode unit. The routines may be fetched by the microprocessor upon occurrence of a corresponding instruction. For example, DSP functions may be fetched upon occurrence of an instruction defined by the microprocessor to be indicative of a DSP function. The microcode unit provides a library of useful functions. Effectively, the instruction set executed by the microprocessor is increased. A number of methods for defining instructions indicative of a DSP function are contemplated. For example, a subroutine call instruction having a target address within a predefined range of addresses may be defined as indicative of a DSP function. Alternatively, a special subroutine call instruction may be added to the instruction set. Detection of the special subroutine call instruction encoding causes the microprocessor to fetch instructions from the microcode unit. A third alternative is to detect data patterns in data movement instructions and cause instructions to be fetched from the microcode unit upon occurrence of particular data patterns. 
Advanced Micro Devices, Inc.
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Thang M.
Tran