Lowe Hauptman & Ham, LLP
System and methods for converting planar design to FinFET design
A method and layout generating machine for generating a layout for a device having FinFETs from a first layout for a device having planar transistors are disclosed. A planar layout with a plurality of FinFET active areas is received and corresponding FinFET active areas are generated with active area widths. Mandrels are generated according to the active area widths and adjusted such that a beta ratio of a beta number for each FinFET active area to a beta number for each corresponding planar active area is within a predetermined beta ratio range.
Taiwan Semiconductor Manufacturing Company, Ltd.
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additional inventional inventional additional
Chien-Wen Shu-Yu Hsiao-Hui Chih-Sheng Yi-Tang Cheok-Kei Clement Hsingjen Yu-Ning
Chen Chen Chen Chang Lin Lei Wann Chang