Arent Fox LLP
Memory device, memory controller and memory system
The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.
Fujitsu Microelectronics Limited
G G
G11C G06F
inventional inventional
Takahiko Hitoshi Hidenaga Tatsuya Ayako Satoru Yoshinobu Hiroyuki Shinnosuke Masanori Tatsushi Tetsuo Toshiya
Sato Ikeda Takahashi Kanda Sato Shirakawa Yamamoto Kobayashi Kamata Kurita Otsuka Miyamoto Uchida