Fish & Richardson P.C.
Memory device and semiconductor device
Provided is a memory device with reduced overhead power. A memory device includes a first circuit retaining data in a first period during which a power supply voltage is supplied; a second circuit saving the data retained in the first circuit in the first period and retaining the data saved from the first circuit in a second period during which the power supply voltage is not supplied; and a third circuit saving the data retained in the second circuit in the second period and retaining the data saved from the second circuit in a third period during which the power supply voltage is not supplied. The third circuit includes a transistor in which a channel formation region is provided in an oxide semiconductor film and a capacitor to which a potential corresponding to the data is supplied through the transistor.
Semiconductor Energy Laboratory Co., Ltd.
G G
G11C G11C
inventional inventional
Takuro Kiyoshi Yasuyuki
Ohmaru Kato Takahashi