Fliesler, Dubb, Meyer & Lovejoy
System for providing tight program/erase speeds that are insensitive to process variations
 The system and method of enhancing the yield of flash memory circuit is disclosed. The method comprises performing a diagonal erase of a select group of memory cells on a wafer during sort. If the memory cells do not erase in a satisfactory manner, the control voltage applied to the memory cell is adjusted based on the memory cell's erase time. The circuitry for providing the adjustment voltage includes trimming circuitry for an incrementally increasing the applicable control of voltage. 
Advanced Micro Devices, Inc.
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Lee E. Jian
Cleveland Chen