JCIPRNET
Memory array structure, in-memory computing apparatus and method thereof
A memory array structure that includes memory columns having first bit lines and second bit lines is introduced. Each of the memory columns includes a bit line pair, a pre-charge switch pair and a first switch pair. Output voltages from the first bit lines and the second bit lines are used to generated a first average voltage and a second average voltage, respectively. One of the first average voltage and the second average voltage is a lower average voltage and another one of the first average voltage and the second average voltage is a higher average voltage. The pre-charge switch pair and the first switch pair of a selected memory column among the plurality of memory columns are controlled to repeatedly perform an incremental step to increment the lower average voltage by a step voltage until the lower average voltage is greater than the higher average voltage.
Taiwan Semiconductor Manufacturing Co., Ltd.
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Jaw-Juinn Yung-Chow Chin-Ho
Horng Peng Chang