Myers Bigel Sibley & Sajovec
Systems and methods for correcting duty cycle deviations in clock and data signals
 A duty cycle-corrected clock signal is generated from a clock signal. A reference signal also is generated that is based upon a duty cycle deviation between the duty cycle-corrected clock signal and the clock signal. Input data is compared to the reference signal in response to the duty cycle-corrected clock signal, to thereby generate duty cycle-corrected output data. Thus, the clock signal and the input data are both duty cycle-corrected to thereby allow an increase in the operating margins of the integrated circuit. The performance and/or speed of the integrated circuit thereby may be increased. 
Samsung Electronics Co., Ltd.
H
H03K
inventional
Jung-hwan
Choi