Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program product
A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
Kabushiki Kaisha Toshiba
G
G06F
inventional
Kazuyuki Takeshi Noriaki Takeshi Masaaki Junichi Kenji Hisashi Motoya
Higashi Fujimaki Matsunaga Nishioka Hatano Wada Yoshida Kaneko Okazaki