Method for selective salicidation of source/drain regions of a transistor
 Selective salicidation of source/drain regions of a transistor is accomplished by performing an implant into a first plurality of transistor source/drain regions on an integrated circuit. As a result of the implant, doping density of the first plurality of transistor source/drain regions is greater than doping density of a second plurality of transistor source/drain regions on the integrated circuit. The integrated circuit is heated to a heating temperature sufficient to produce oxidation regions immediately over the first plurality of transistor source/drain regions and the second plurality of transistor source/drain regions. The heating temperature is chosen so that the oxidation regions immediately over the first plurality of transistor source/drain regions are thicker than the oxidation regions immediately over the second plurality of transistor source/drain regions. A metal layer is formed over the first plurality of transistor source/drain regions and the second plurality of transistor source/drain regions. The metal layer is annealed at a temperature such that the metal reacts to form metal-silicide over the second plurality of transistor source/drain regions, but not over the first plurality of transistor source/drain regions. The unreacted metal is stripped off over the first plurality of transistor source/drain regions. 
VLSI Technology, Inc.
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Tiao-Yuan
Huang