Schwabe, Williamson & Wyatt, P.C.
Multiple stacked field-plated GaN transistor and interlayer dielectrics to improve breakdown voltage and reduce parasitic capacitances
Embodiments of the invention include a high voltage transistor with one or more field plates and methods of forming such transistors. According to an embodiment, the transistor may include a source region, a drain region, and a gate electrode formed over a channel region formed between the source region and drain region. Embodiments of the invention may also include a first interlayer dielectric (ILD) formed over the channel region and a second ILD formed over the first ILD. According to an embodiment, a first field plate may be formed in the second ILD. In an embodiment the first field plate is not formed as a single bulk conductive feature with the gate electrode. In some embodiments, the first field plate may be electrically coupled to the gate electrode by one or more vias. In alternative embodiments, the first field plate may be electrically isolated from the gate electrode.
Intel Corporation
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Marko Seung Hoon Han Wui Sansaptak Sanaz K.
Radosavljevic Sung Then Dasgupta Gardner