Slater Matsil, LLP
Method and apparatus for asynchronous processor pipeline and bypass passing
A clock-less asynchronous processor comprising a plurality of parallel asynchronous processing logic circuits, each processing logic circuit configured to generate an instruction execution result. The processor comprises an asynchronous instruction dispatch unit coupled to each processing logic circuit, the instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the processing logic circuits. The processor comprises a crossbar coupled to an output of each processing logic circuit and to the dispatch unit, the crossbar configured to store the instruction execution results.
Huawei Technologies Co., Ltd.
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Wuxian Tao Wen Qifan Yiqun
Shi Huang Tong Zhang Ge