Haynes and Boone, LLP
Method and structure for mandrel and spacer patterning
A method includes receiving an integrated circuit design layout that includes first and second layout blocks separated by a first space. The first and second layout blocks include, respectively, first and second line patterns oriented lengthwise in a first direction. The method further includes adding a dummy pattern to the first space, which connects the first and second line patterns. The method further includes outputting a mandrel pattern layout and a cut pattern layout in a computer-readable format. The mandrel pattern layout includes the first and second line patterns and the dummy pattern. The cut pattern layout includes a pattern corresponding to the first space. In embodiments, the method further includes manufacturing a first mask with the mandrel pattern layout and manufacturing a second mask with the cut pattern layout. In embodiments, the method further includes patterning a substrate with the first mask and the second mask.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
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Shih-Chi Kuei-Shun Chih-Hsiung Chi-Kang Chung-Ming
Fu Chen Peng Chang Wang