Haynes and Boone, LLP
Grid refinement method
The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Burn Jeng Pei-Yi Jaw-Jung Wen-Chuan Shy-Jay
Lin Liu Shin Wang Lin