Nicholson De Vos Webster & Elliott LLP
Apparatuses and methods to prevent execution of a modified instruction
Methods and apparatuses relating to preventing the execution of a modified instruction. In one embodiment, an apparatus includes a hardware binary translator to translate an instruction to a translated instruction, and a consistency hardware manager to prevent execution of the translated instruction by a hardware processor on detection of a modification to a virtual to physical address mapping of the instruction after the translation.
INTEL CORPORATION
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Polychronis Jason M. Jamison D.
Xekalakis Agron Collins