Finnegan, Henderson, Farabow, Garrett & Dunner
High-speed semiconductor device
 A CMOS semiconductor memory device in which a memory cell array and peripheral circuits are formed on the same semiconductor substrate. Wells of the peripheral circuits with MOS transistors of one channel type formed therein are supplied with a PN junction reverse bias potential higher than that for wells of the memory cell array during the memory operation, while the potential at the peripheral circuit wells is made equal to the potential at the wells of the memory cell array when the memory is not operating. High-speed operation of the memory device may be achieved because the junction capacitance of the MOS transistors formed in the peripheral circuit wells is reduced when the memory is operating. 
Tokyo Shibaura Denki Kabushiki Kaisha
G H H H H
G11C H01L H01L H01L H01L
inventional inventional additional inventional additional
Kiyofumi Hirozi Yasoji
Ochii Asahi Suzuki