Hauptman Ham, LLP
Apparatus and method for integrated circuit bit line sharing
A memory array includes a first memory column having a first bit line, a first word line and a second bit line. The memory array also includes a second memory column having the second bit line, a second word line and a third bit line. The first memory column and the second memory column are configured to share the second bit line. The sharing of the second bit line facilitates sharing one or more memory array components between the first memory column and the second memory column.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
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Geng-Cing Cheng-Jen Yi-Tzu Hao-I Yu-Hao
Lin Chang Chen Yang Hu