Blakely, Sokoloff, Taylor & Zafman LLP
Apparatus and method for performing multi-dimensional computations based on intra-add operation
 A method and apparatus for including in a processor, instructions for performing multiply-intra-add operations on packed data is described. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first and a second packed data. The processor performs operations on data elements in the first packed data and the second packed data to generate a plurality of data elements in a third packed data in response to receiving an instruction. At least two of the plurality of data elements in the third packed data store the result of multiply-intra-add operations. 
Intel Corporation
G G
G06F G06F
inventional inventional
Patrice L.
Roussel