Finnegan, Henderson, Farabow, Garrett & Dunner
MOS Integrated circuit
 A MOS integrated circuit including P-channel MOS transistors, particularly for C-MOS inverter, in which the P-channel MOS transistor (12) has P.sup.+ drain (34), P.sup.+ source (36) connected to a +VDD circuit (42) via P.sup.+ and N.sup.+ diffusion layers (36.sub.1, 36.sub.2) and isolation gate (38). The P.sup.+ layer is partly replaced by, i.e. parallel- and/or serial-connected to the N.sup.+ layer so that an effective source diffusion resistance (R.sub.S) or the conductive resistance (R.sub.0) is lowered. 
Tokyo Shibaura Denki Kabushiki Kaisha
H
H01L
inventional
Yasoji Yasushi Hiroshi Minoru
Suzuki Satoh Osanai Takada