McClure, Qualey & Rodack, LLP
3-D memory and built-in self-test circuit thereof
A three-dimensional (3-D) memory includes: multiple memory dies, each having at least one memory bank and a built-in self-test (BIST) circuit; and a plurality of channels, for electrically connecting the memory dies. In a synchronous test, one of the memory dies is selected as a master die. The BIST circuit of the master die sends an enable signal via the channels to the memory dies under test. The BIST circuit in each of the memory dies is for testing memory banks on the same memory die or on different memory dies.
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
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G11C G11C G11C
inventional inventional inventional
Ding-Ming Yun-Chao Che-Wei Chih-Yen Jin-Fu
Kwai Yu Chou Lo Li