Lowe Hauptman & Ham, LLP
Glitch free oversampling clock and data recovery
A clock and data recovery (CDR) circuit includes an edge detector, an edge selector, and a phase selector. The edge detector is arranged to detect edges of serial input data and to provide an edge detection result. The serial input data is oversampled utilizing multiple clock phases. The edge selector for selecting one of the multiple clock phases for a recovered clock is arranged to provide an edge selection result, to receive the last edge selection result as a first input, and to receive the edge detection result as a second input. The phase selector is arranged to provide the recovered clock and recovered data.
Taiwan Semiconductor Manufacturing Company, Ltd.
H
H04L
inventional
Yu-Chi
Chen