Jianq Chyun IP Office
Via structure, memory array structure, three-dimensional resistance memory and method of forming the same
Provided is a three-dimensional resistance memory including a stack of layers. The stack of layers is encapsulated in a dielectric layer and is adjacent to at least one opening in the encapsulating dielectric layer. At least one L-shaped variable resistance spacer is disposed on at least a portion of the sidewall of the opening adjacent to the stack of layers. An electrode layer fills the remaining portion of the opening.
Industrial Technology Research Institute
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Frederick T. Tai-Yuan Wei-Su Yu-Sheng Yu-De Pei-Yi
Chen Wu Chen Chen Lin Gu