Tutunjian & Bitetto, P.C.
Vertical field effect transistor with reduced gate to source/drain capacitance
A method of forming a fin field effect transistor device is provided. The method includes forming a vertical fin layer on a bottom source/drain layer, and forming one or more fin templates on the vertical fin layer. The method further includes forming a vertical fin below each of the one or more fin templates. The method further includes reducing the width of each of the vertical fins to form one or more thinned vertical fins, wherein at least a portion of the fin template overhangs the sides of the underlying thinned vertical fin. The method further includes depositing a bottom spacer layer on the bottom source/drain layer, wherein the bottom spacer layer has a non-uniform thickness that tapers in a direction towards the thinned vertical fins.
INTERNATIONAL BUSINESS MACHINES CORPORATION
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Choonghyun Peng Kangguo Juntao
Lee Xu Cheng Li