Calibrated SAR ADC having a reduced size
The silicon real estate required for the semiconductor fabrication of a calibrated capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) (100) is substantially reduced by using a number of shared capacitors (SC1-SCs−1) which are used as calibration capacitors when operating in a calibration mode and as bit capacitors when operating in a normal mode.
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inventional inventional additional inventional inventional
Ajit Sriram Arup Seung Bae Srinath Mathur
Sharma Narayanan Polley Lee Ramaswamy