Warn, Hoffmann, Miller & LaLone, P.C.
High power chip scale package
A packaged die (112) for an integrated circuit (62) that eliminates the wire bonds required in the prior art, and provides integrated circuit packaging while the circuit (62) is still in a wafer format. A wafer substrate (64) on which the integrated circuits (62) have been fabricated is patterned and etched to form signal and ground vias (74, 72) through the substrate (64). A back-side ground plane (82) is deposited in contact with the ground vias (72). A protective layer (90) is formed on the top surface (76) of the substrate (64), and a protective layer (98) is formed on the bottom surface (84) of the substrate (64), where the bottom protective layer (98) fills in removed substrate material between the integrated circuits (62). Vias (106) are formed through the bottom protective layer (98), and the wafer substrate (64) is diced between the integrated circuits (62).
Northrop Grumman Corporation
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James Gershon
Anderson Akerling