Jianq Chyun IP Office
Leakage testing method for dynamic random access memory having a recess gate
A leakage testing method for a DRAM having a recess gate is provided. The method includes the steps of: programming to set the first storage unit and the second storage unit of a same memory cell with different storage statuses; and disturbing one of the word lines extending through the memory cells; then determining whether the DRAM is acceptable or not. When another one of the word lines extending through the memory cells is caused with a reading error by disturbing the one of the word lines extending through the memory cells, a failure is determined as occurred, and the failure is attributed to a leakage type of extended depletion region. When the another one of the word lines extending through the memory cells is not caused with a reading error by disturbing the one of the word lines extending through the memory cells, the DRAM is determined as acceptable.
ProMOS Technologies Inc.
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inventional inventional additional additional inventional
Ming Hsieh Che-Yi Yuan-Hwa Chung-Yuan
Tsai Hsu Lee Chang