Haynes and Boone, LLP
Lithography process
A process for use in lithography, such as photolithography for patterning a semiconductor wafer, is disclosed. The process includes receiving an incoming semiconductor wafer having various features and layers formed thereon. A unit-induced overlay (uniiOVL) correction is received and a deformation measurement is performed on the incoming semiconductor wafer in an overlay module. A deformation-induced overlay (defiOVL) correction is generated from the deformation measurement results by employing a predetermined algorithm on the deformation measurement results. The defiOVL and uniiOVL corrections are fed-forward to an exposure module and an exposure process is performed on the incoming semiconductor wafer.
Taiwan Semiconductor Manufacturing Company, Ltd.
G
G03F
inventional
Ying Ying Heng-Hsin Yung-Yao Chin-Hsiang
Wang Liu Lee Lin