Analog delay cell having continuous adjustable delay time
A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.
UNITED MICROELECTRONICS CORP.
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additional inventional additional
Wei-Jen Yuan-Hui Cheng-Tsung Kun-Yuan Yu-Lin Chien-Fu Cheng-Yang Zhi-Hong Chen-Hsien Ruei-Yau
Wang Chen Ku Wu Chen Chen Tsai Huang Hsu Chen