JCIPRNET
Semiconductor package and manufacturing method thereof
A semiconductor package includes a first chip package including a plurality of first semiconductor dies and a first insulating encapsulant, a second semiconductor die, a third semiconductor die, and a second insulating encapsulant. The plurality of first semiconductor dies are electrically connected to each other, and the first insulating encapsulant encapsulates the plurality of first semiconductor dies. The second semiconductor die and the third semiconductor die are electrically communicated to each other by connecting to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die. The second insulating encapsulant encapsulates the first chip package, the second semiconductor die, and the third semiconductor die.
Taiwan Semiconductor Manufacturing Company, Ltd.
H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H
H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L
additional inventional additional additional additional inventional inventional inventional inventional additional additional additional additional additional inventional additional additional additional inventional inventional inventional additional inventional additional additional additional inventional additional additional inventional additional inventional inventional inventional additional inventional additional
Hsien-Wei Jie
Chen Chen