Dummy patterns and method for generating dummy patterns
A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns.
UNITED MICROELECTRONICS CORP.
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Hsiang Chin-Yueh Yao-Jen Jian-Cheng Heng-Kun Chen-Hua
Yang Tsai Fan Chen Chen Tsai