Oliff & Berridge, PLC
Layered chip package and method of manufacturing same
A layered chip package includes a main body and wiring, the wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a main part and a plurality of terminals. The main part includes a plurality of layer portions stacked. The terminals are disposed on at least either one of the top and bottom surfaces of the main part and electrically connected to the wires. Each of the layer portions includes a semiconductor chip. The plurality of wires include a plurality of common wires and a plurality of layer-dependent wires. In at least one of the layer portions, the semiconductor chip is electrically connected to the plurality of common wires and is selectively electrically connected to only the layer-dependent wire that the layer portion uses, among the plurality of layer-dependent wires.
SAE Magnetics H.K., Ltd. Headway Technologies, Inc.
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Hiroyuki Yoshitaka Hiroshi Atsushi
Ito Sasaki Ikejima Iijima