Vierra Magen Marcus LLP
Reducing post-read disturb in a nonvolatile memory device
An apparatus includes a plurality of NAND strings in a block with word lines connected to cells of the NAND strings and select lines connected to select gate transistors of the NAND strings. A control circuit is configured to, after a read operation of memory cells of the block apply substantially zero volts to the global word lines to discharge the word lines to substantially zero volts. The control circuit is further configured to turn off the select gate transistors to isolate channels, turn off the block select transistors to isolate the word lines from the global word lines, and with the block select transistors turned off, apply a low positive voltage on the global word lines.
Western Digital Technologies, Inc.
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Abhijith Dengtao Deepanshu Huai-Yuan Wei Anubhav
Prakash Zhao Dutta Tseng Zhao Khandelwal