Finnegan, Henderson, Farabow & Garrett
Semiconductor memory device to reduce parasitic output capacitance
 A semiconductor memory device includes a memory circuit formed of a plurality of matrix-arranged memory cells, a plurality of output data lines, each of which is connected to memory cells arranged in the same column of the matrix memory circuit, and a plurality of data-sensing circuits for delivering output data from the matrix memory circuit to an output device. The data-sensing circuits are divided into a plurality of groups, and the semiconductor memory device further comprises clocked inverters whose input terminals are connected to the output terminals of the respective groups of sensing circuits and whose output terminals are connected to the output device, and a control circuit which, when one of the data-sensing circuits issues an output, supplies an energizing signal to that of the clocked inverters which is connected to said one data-sensing circuit. 
Tokyo Shibaura Electric Co., Ltd.
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inventional inventional inventional inventional
Yasoji Kiyofumi
Suzuki Ochii