Antonelli, Terry, Stout & Kraus, LLP
Semiconductor integrated circuit apparatus
 The present invention is intended to provide a conventional circuit apparatus which is highly tolerant to noises and operates at a higher speed than a completely complementary static CMOS circuit. To achieve this, circuit apparatus according to the present invention is provided with a plurality of CMOS static logic circuits which are series-connected and potential setting means which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore circuit operation is speeded up and .alpha. particle noise and noises due to charge redistribution effect or leakage current can be prevented. 
Hitachi, Ltd.
H
H03K
inventional
Takashi Fumio Tatsumi Hiromichi
Hotta Murabayashi Yamauchi Yamada