Eschweiler & Potashnik, LLC
Techniques for wafer stack processing
The present disclosure relates to a method for forming a multi-dimensional integrated chip structure. In some embodiments, the method may be performed by bonding a second substrate to an upper surface of a first substrate. A first edge trimming cut is performed along a first loop and extends into a first peripheral portion of the second substrate. A second edge trimming cut is performed along a second loop and extends into a second peripheral portion of the second substrate and into the first substrate. A third edge trimming cut is performed along a third loop and extends into a third peripheral portion of the first substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.
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Hau-Yi Yung-Lung Cheng-Hsien Kuo-Ming Cheng-Yuan
Hsiao Lin Chou Wu Tsai