Jianq Chyun IP Office
Semiconductor package and manufacturing method thereof
A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution layer, a second redistribution layer, and a plurality of through interlayer vias. The molded semiconductor device includes a die. The first redistribution layer is disposed on a first side of the molded semiconductor device. The second redistribution layer is disposed on a second side of the molded semiconductor device opposite to the first side, wherein the second redistribution layer includes a patterned metal layer having an interconnection circuit portion electrically connected to the die and a metal ring surrounding and insulated from the interconnection circuit portion. The through interlayer vias are located right under the metal ring and extending through the molded semiconductor device to be electrically connect the first redistribution layer and the second redistribution layer.
Taiwan Semiconductor Manufacturing Co., Ltd.
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Chih-Wei Yu-Jen Yu-Feng Yu-Chih Chih-Hsuan Hao-Yi Chih-Hua
Lin Cheng Chen Huang Tai Tsai Chen