WPAT, PC
Memory signal phase difference calibration circuit and method
A memory signal phase difference calibration circuit includes: a clock generator providing clocks allowing a physical layer (PHY) circuit of DDR SDRAM to generate a data input/output signal (DQ) and a data strobe signal (DQS) for accessing a storage circuit; a calibration control circuit outputting a phase control signal according to an adjustment range to adjust the phase of a target signal (DQ or DQS), and outputting a calibration control signal; an access control circuit reading storage data representing predetermined data from the storage circuit according to the calibration control signal; a comparison circuit comparing the predetermined data with the storage data to output a result allowing the calibration control circuit to alter the adjustment range accordingly; and a phase controller outputting a clock control signal according to the phase control signal to set the phase of a target clock used for the PHY circuit generating the target signal.
REALTEK SEMICONDUCTOR CORPORATION
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Shih-Han Chun-Chi Gerchih Chih-Wei Fu-Chin
Lin Yu Chou Chang Tsai