Schwabe, Williamson & Wyatt, P.C.
Dual-layer dielectric in memory device
Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.
Intel Corporation
H H H H H H H H H H H H H H H H
H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L H01L
inventional inventional additional inventional inventional inventional additional inventional additional inventional inventional inventional inventional inventional additional additional
Yudong Tuman Earl Michael J. Kevin Lee Ronald Allen Denzil S. Kolya
Kim Allen, III Bernhardt Baker Weimer Frost Yastrebenetsky