Keyhole-free process for high aspect ratio gap filing
 A method to eliminate voids in the dielectric oxide between closely spaced conducting lines is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A high density plasma (HDP) dielectric layer is deposited overlying the conductive lines and the substrate. The HDP layer is etched through to expose the edges of the conducting lines. An insulating layer is deposited overlying the HDP layer and conducting lines. A chemical mechanical polishing (CMP) is used to remove the peaks of the insulating layer, exposing the HDP layer in the area overlying the conducting lines. The exposed HDP layer is etched away exposing the top surface of the conducting lines. The insulating layer is then selectively etched away. Spacers may then be added along the sidewalls of the conductor. Finally, a second HDP layer is deposited overlying the first dielectric layer and conducting lines free from voids. The integrated circuit device is completed. 
Taiwan Semiconductor Manufacturing Company
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Cheng-Ming Yu-Hua
Wu Lee