F. Chau & Associates, LLP
Mode selection circuit for semiconductor memory device
A mode selection circuit for a semiconductor memory device includes a timing register for generating first and second control signals in response to a command signal and a first address signal, a programming control signal generator for generating third control signals in response to a second address signal and the first control signal, and a mode selection signal generator for generating mode selection signals in response to a master signal, the second control signal, and the third control signals, wherein the mode selection signals are activated in accordance with a sequential order of activation of the third control signals.
Samsung Electronics Co., Ltd.
G
G11C
inventional
Yun-Sang Jong-Hyun Sang-Seok Kyu-Nam
Lee Choi Kang Lim